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17743bc712
Parametrise the AXI interface of CVA6. With this PR, both cache subsystems support variable AXI address widths. The write-through cache furthermore supports variable AXI data widths. Moreover, this PR includes a modular AXI testbench for the WT cache to test the introduced changes. The following configurations of the WT cache have been verified: XLEN Cacheline Width AXI data width AXI address width 64 128 64 64 64 128 128 52 64 512 128 64 32 512 256 48 32 64 32 48
302 lines
11 KiB
Systemverilog
302 lines
11 KiB
Systemverilog
/* Copyright 2018 ETH Zurich and University of Bologna.
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* Copyright and related rights are licensed under the Solderpad Hardware
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* License, Version 0.51 (the “License”); you may not use this file except in
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* compliance with the License. You may obtain a copy of the License at
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* http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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* or agreed to in writing, software, hardware and materials distributed under
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* this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
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* CONDITIONS OF ANY KIND, either express or implied. See the License for the
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* specific language governing permissions and limitations under the License.
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*
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* File: axi_shim.sv
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* Author: Michael Schaffner <schaffner@iis.ee.ethz.ch>
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* Florian Zaruba <zarubaf@iis.ee.ethz.ch>
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* Date: 1.8.2018
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*
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* Description: Manages communication with the AXI Bus. Note that this unit does not
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* buffer requests and register the signals.
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*
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*/
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module axi_shim #(
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parameter int unsigned AxiUserWidth = 64, // data width in dwords, this is also the maximum burst length, must be >=2
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parameter int unsigned AxiNumWords = 4, // data width in dwords, this is also the maximum burst length, must be >=2
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parameter int unsigned AxiAddrWidth = 0,
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parameter int unsigned AxiDataWidth = 0,
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parameter int unsigned AxiIdWidth = 0,
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parameter type axi_req_t = ariane_axi::req_t,
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parameter type axi_rsp_t = ariane_axi::resp_t
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) (
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input logic clk_i, // Clock
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input logic rst_ni, // Asynchronous reset active low
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// read channel
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// request
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input logic rd_req_i,
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output logic rd_gnt_o,
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input logic [AxiAddrWidth-1:0] rd_addr_i,
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input logic [$clog2(AxiNumWords)-1:0] rd_blen_i, // axi convention: LEN-1
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input logic [2:0] rd_size_i,
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input logic [AxiIdWidth-1:0] rd_id_i, // use same ID for reads, or make sure you only have one outstanding read tx
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input logic rd_lock_i,
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// read response (we have to unconditionally sink the response)
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input logic rd_rdy_i,
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output logic rd_last_o,
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output logic rd_valid_o,
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output logic [AxiDataWidth-1:0] rd_data_o,
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output logic [AxiUserWidth-1:0] rd_user_o,
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output logic [AxiIdWidth-1:0] rd_id_o,
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output logic rd_exokay_o, // indicates whether exclusive tx succeeded
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// write channel
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input logic wr_req_i,
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output logic wr_gnt_o,
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input logic [AxiAddrWidth-1:0] wr_addr_i,
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input logic [AxiNumWords-1:0][AxiDataWidth-1:0] wr_data_i,
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input logic [AxiNumWords-1:0][AxiUserWidth-1:0] wr_user_i,
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input logic [AxiNumWords-1:0][(AxiDataWidth/8)-1:0] wr_be_i,
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input logic [$clog2(AxiNumWords)-1:0] wr_blen_i, // axi convention: LEN-1
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input logic [2:0] wr_size_i,
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input logic [AxiIdWidth-1:0] wr_id_i,
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input logic wr_lock_i,
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input logic [5:0] wr_atop_i,
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// write response
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input logic wr_rdy_i,
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output logic wr_valid_o,
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output logic [AxiIdWidth-1:0] wr_id_o,
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output logic wr_exokay_o, // indicates whether exclusive tx succeeded
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// AXI port
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output axi_req_t axi_req_o,
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input axi_rsp_t axi_resp_i
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);
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localparam AddrIndex = ($clog2(AxiNumWords) > 0) ? $clog2(AxiNumWords) : 1;
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///////////////////////////////////////////////////////
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// write channel
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///////////////////////////////////////////////////////
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enum logic [3:0] {
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IDLE, WAIT_AW_READY, WAIT_LAST_W_READY, WAIT_LAST_W_READY_AW_READY, WAIT_AW_READY_BURST
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} wr_state_q, wr_state_d;
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// AXI tx counter
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logic [AddrIndex-1:0] wr_cnt_d, wr_cnt_q;
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logic wr_single_req, wr_cnt_done, wr_cnt_clr, wr_cnt_en;
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assign wr_single_req = (wr_blen_i == 0);
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// address
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assign axi_req_o.aw.burst = axi_pkg::BURST_INCR; // Use BURST_INCR for AXI regular transaction
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assign axi_req_o.aw.addr = wr_addr_i[AxiAddrWidth-1:0];
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assign axi_req_o.aw.size = wr_size_i;
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assign axi_req_o.aw.len = wr_blen_i;
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assign axi_req_o.aw.id = wr_id_i;
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assign axi_req_o.aw.prot = 3'b0;
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assign axi_req_o.aw.region = 4'b0;
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assign axi_req_o.aw.lock = wr_lock_i;
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assign axi_req_o.aw.cache = 4'b0;
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assign axi_req_o.aw.qos = 4'b0;
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assign axi_req_o.aw.atop = wr_atop_i;
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assign axi_req_o.aw.user = '0;
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// data
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assign axi_req_o.w.data = wr_data_i[wr_cnt_q];
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assign axi_req_o.w.user = wr_user_i[wr_cnt_q];
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assign axi_req_o.w.strb = wr_be_i[wr_cnt_q];
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assign axi_req_o.w.last = wr_cnt_done;
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// write response
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assign wr_exokay_o = (axi_resp_i.b.resp == axi_pkg::RESP_EXOKAY);
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assign axi_req_o.b_ready = wr_rdy_i;
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assign wr_valid_o = axi_resp_i.b_valid;
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assign wr_id_o = axi_resp_i.b.id;
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// tx counter
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assign wr_cnt_done = (wr_cnt_q == wr_blen_i);
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assign wr_cnt_d = (wr_cnt_clr) ?
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'0 : (wr_cnt_en) ?
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wr_cnt_q+1 : wr_cnt_q;
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always_comb begin : p_axi_write_fsm
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// default
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wr_state_d = wr_state_q;
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axi_req_o.aw_valid = 1'b0;
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axi_req_o.w_valid = 1'b0;
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wr_gnt_o = 1'b0;
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wr_cnt_en = 1'b0;
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wr_cnt_clr = 1'b0;
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case (wr_state_q)
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///////////////////////////////////
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IDLE: begin
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// we have an incoming request
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if (wr_req_i) begin
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// is this a read or write?
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axi_req_o.aw_valid = 1'b1;
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axi_req_o.w_valid = 1'b1;
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// its a single write
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if (wr_single_req) begin
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wr_cnt_clr = 1'b1;
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// single req can be granted here
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wr_gnt_o = axi_resp_i.aw_ready & axi_resp_i.w_ready;
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case ({axi_resp_i.aw_ready, axi_resp_i.w_ready})
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2'b01: wr_state_d = WAIT_AW_READY;
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2'b10: wr_state_d = WAIT_LAST_W_READY;
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default: wr_state_d = IDLE;
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endcase
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// its a request for the whole cache line
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end else begin
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wr_cnt_en = axi_resp_i.w_ready;
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case ({axi_resp_i.aw_ready, axi_resp_i.w_ready})
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2'b11: wr_state_d = WAIT_LAST_W_READY;
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2'b01: wr_state_d = WAIT_LAST_W_READY_AW_READY;
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2'b10: wr_state_d = WAIT_LAST_W_READY;
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default:;
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endcase
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end
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end
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end
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///////////////////////////////////
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// ~> from single write
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WAIT_AW_READY: begin
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axi_req_o.aw_valid = 1'b1;
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if (axi_resp_i.aw_ready) begin
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wr_state_d = IDLE;
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wr_gnt_o = 1'b1;
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end
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end
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///////////////////////////////////
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// ~> we need to wait for an aw_ready and there is at least one outstanding write
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WAIT_LAST_W_READY_AW_READY: begin
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axi_req_o.w_valid = 1'b1;
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axi_req_o.aw_valid = 1'b1;
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// we got an aw_ready
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case ({axi_resp_i.aw_ready, axi_resp_i.w_ready})
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// we got an aw ready
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2'b01: begin
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// are there any outstanding transactions?
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if (wr_cnt_done) begin
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wr_state_d = WAIT_AW_READY_BURST;
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wr_cnt_clr = 1'b1;
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end else begin
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// yes, so reduce the count and stay here
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wr_cnt_en = 1'b1;
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end
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end
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2'b10: wr_state_d = WAIT_LAST_W_READY;
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2'b11: begin
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// we are finished
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if (wr_cnt_done) begin
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wr_state_d = IDLE;
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wr_gnt_o = 1'b1;
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wr_cnt_clr = 1'b1;
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// there are outstanding transactions
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end else begin
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wr_state_d = WAIT_LAST_W_READY;
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wr_cnt_en = 1'b1;
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end
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end
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default:;
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endcase
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end
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///////////////////////////////////
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// ~> all data has already been sent, we are only waiting for the aw_ready
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WAIT_AW_READY_BURST: begin
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axi_req_o.aw_valid = 1'b1;
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if (axi_resp_i.aw_ready) begin
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wr_state_d = IDLE;
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wr_gnt_o = 1'b1;
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end
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end
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///////////////////////////////////
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// ~> from write, there is an outstanding write
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WAIT_LAST_W_READY: begin
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axi_req_o.w_valid = 1'b1;
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// this is the last write
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if (wr_cnt_done) begin
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if (axi_resp_i.w_ready) begin
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wr_state_d = IDLE;
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wr_cnt_clr = 1'b1;
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wr_gnt_o = 1'b1;
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end
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end else if (axi_resp_i.w_ready) begin
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wr_cnt_en = 1'b1;
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end
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end
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///////////////////////////////////
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default: begin
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wr_state_d = IDLE;
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end
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endcase
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end
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///////////////////////////////////////////////////////
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// read channel
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///////////////////////////////////////////////////////
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// address
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// in case of a wrapping transfer we can simply begin at the address, if we want to request a cache-line
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// with an incremental transfer we need to output the corresponding base address of the cache line
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assign axi_req_o.ar.burst = axi_pkg::BURST_INCR; // Use BURST_INCR for AXI regular transaction
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assign axi_req_o.ar.addr = rd_addr_i[AxiAddrWidth-1:0];
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assign axi_req_o.ar.size = rd_size_i;
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assign axi_req_o.ar.len = rd_blen_i;
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assign axi_req_o.ar.id = rd_id_i;
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assign axi_req_o.ar.prot = 3'b0;
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assign axi_req_o.ar.region = 4'b0;
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assign axi_req_o.ar.lock = rd_lock_i;
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assign axi_req_o.ar.cache = 4'b0;
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assign axi_req_o.ar.qos = 4'b0;
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assign axi_req_o.ar.user = '0;
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// make the read request
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assign axi_req_o.ar_valid = rd_req_i;
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assign rd_gnt_o = rd_req_i & axi_resp_i.ar_ready;
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// return path
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assign axi_req_o.r_ready = rd_rdy_i;
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assign rd_data_o = axi_resp_i.r.data;
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assign rd_user_o = axi_resp_i.r.user;
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assign rd_last_o = axi_resp_i.r.last;
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assign rd_valid_o = axi_resp_i.r_valid;
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assign rd_id_o = axi_resp_i.r.id;
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assign rd_exokay_o = (axi_resp_i.r.resp == axi_pkg::RESP_EXOKAY);
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// ----------------
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// Registers
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// ----------------
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (~rst_ni) begin
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// start in flushing state and initialize the memory
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wr_state_q <= IDLE;
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wr_cnt_q <= '0;
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end else begin
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wr_state_q <= wr_state_d;
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wr_cnt_q <= wr_cnt_d;
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end
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end
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// ----------------
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// Assertions
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// ----------------
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//pragma translate_off
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`ifndef VERILATOR
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initial begin
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assert (AxiNumWords >= 1) else
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$fatal(1, "[axi adapter] AxiNumWords must be >= 1");
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assert (AxiIdWidth >= 2) else
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$fatal(1, "[axi adapter] AXI id width must be at least 2 bit wide");
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end
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`endif
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//pragma translate_on
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endmodule // axi_adapter2
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