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0b61544da8
Reduce dcache data output width from 64 to 32 bits in cv32a6 configuration Signed-off-by: sjthales <sebastien.jacq@thalesgroup.com>
279 lines
14 KiB
Systemverilog
279 lines
14 KiB
Systemverilog
// Copyright 2018 ETH Zurich and University of Bologna.
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// Copyright and related rights are licensed under the Solderpad Hardware
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// License, Version 0.51 (the "License"); you may not use this file except in
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// compliance with the License. You may obtain a copy of the License at
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// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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// or agreed to in writing, software, hardware and materials distributed under
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// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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// CONDITIONS OF ANY KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations under the License.
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//
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// Author: Florian Zaruba, ETH Zurich
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// Date: 25.04.2017
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// Description: Store queue persists store requests and pushes them to memory
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// if they are no longer speculative
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module store_buffer import ariane_pkg::*; (
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input logic clk_i, // Clock
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input logic rst_ni, // Asynchronous reset active low
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input logic flush_i, // if we flush we need to pause the transactions on the memory
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// otherwise we will run in a deadlock with the memory arbiter
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output logic no_st_pending_o, // non-speculative queue is empty (e.g.: everything is committed to the memory hierarchy)
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output logic store_buffer_empty_o, // there is no store pending in neither the speculative unit or the non-speculative queue
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input logic [11:0] page_offset_i, // check for the page offset (the last 12 bit if the current load matches them)
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output logic page_offset_matches_o, // the above input page offset matches -> let the store buffer drain
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input logic commit_i, // commit the instruction which was placed there most recently
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output logic commit_ready_o, // commit queue is ready to accept another commit request
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output logic ready_o, // the store queue is ready to accept a new request
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// it is only ready if it can unconditionally commit the instruction, e.g.:
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// the commit buffer needs to be empty
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input logic valid_i, // this is a valid store
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input logic valid_without_flush_i, // just tell if the address is valid which we are current putting and do not take any further action
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input logic [riscv::PLEN-1:0] paddr_i, // physical address of store which needs to be placed in the queue
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input riscv::xlen_t data_i, // data which is placed in the queue
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input logic [(riscv::XLEN/8)-1:0] be_i, // byte enable in
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input logic [1:0] data_size_i, // type of request we are making (e.g.: bytes to write)
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// D$ interface
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input dcache_req_o_t req_port_i,
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output dcache_req_i_t req_port_o
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);
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// the store queue has two parts:
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// 1. Speculative queue
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// 2. Commit queue which is non-speculative, e.g.: the store will definitely happen.
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struct packed {
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logic [riscv::PLEN-1:0] address;
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riscv::xlen_t data;
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logic [(riscv::XLEN/8)-1:0] be;
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logic [1:0] data_size;
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logic valid; // this entry is valid, we need this for checking if the address offset matches
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} speculative_queue_n [DEPTH_SPEC-1:0], speculative_queue_q [DEPTH_SPEC-1:0],
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commit_queue_n [DEPTH_COMMIT-1:0], commit_queue_q [DEPTH_COMMIT-1:0];
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// keep a status count for both buffers
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logic [$clog2(DEPTH_SPEC):0] speculative_status_cnt_n, speculative_status_cnt_q;
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logic [$clog2(DEPTH_COMMIT):0] commit_status_cnt_n, commit_status_cnt_q;
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// Speculative queue
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logic [$clog2(DEPTH_SPEC)-1:0] speculative_read_pointer_n, speculative_read_pointer_q;
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logic [$clog2(DEPTH_SPEC)-1:0] speculative_write_pointer_n, speculative_write_pointer_q;
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// Commit Queue
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logic [$clog2(DEPTH_COMMIT)-1:0] commit_read_pointer_n, commit_read_pointer_q;
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logic [$clog2(DEPTH_COMMIT)-1:0] commit_write_pointer_n, commit_write_pointer_q;
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assign store_buffer_empty_o = (speculative_status_cnt_q == 0) & no_st_pending_o;
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// ----------------------------------------
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// Speculative Queue - Core Interface
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// ----------------------------------------
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always_comb begin : core_if
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automatic logic [DEPTH_SPEC:0] speculative_status_cnt;
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speculative_status_cnt = speculative_status_cnt_q;
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// we are ready if the speculative and the commit queue have a space left
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ready_o = (speculative_status_cnt_q < (DEPTH_SPEC - 1)) || commit_i;
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// default assignments
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speculative_status_cnt_n = speculative_status_cnt_q;
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speculative_read_pointer_n = speculative_read_pointer_q;
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speculative_write_pointer_n = speculative_write_pointer_q;
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speculative_queue_n = speculative_queue_q;
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// LSU interface
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// we are ready to accept a new entry and the input data is valid
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if (valid_i) begin
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speculative_queue_n[speculative_write_pointer_q].address = paddr_i;
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speculative_queue_n[speculative_write_pointer_q].data = data_i;
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speculative_queue_n[speculative_write_pointer_q].be = be_i;
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speculative_queue_n[speculative_write_pointer_q].data_size = data_size_i;
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speculative_queue_n[speculative_write_pointer_q].valid = 1'b1;
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// advance the write pointer
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speculative_write_pointer_n = speculative_write_pointer_q + 1'b1;
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speculative_status_cnt++;
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end
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// evict the current entry out of this queue, the commit queue will thankfully take it and commit it
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// to the memory hierarchy
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if (commit_i) begin
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// invalidate
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speculative_queue_n[speculative_read_pointer_q].valid = 1'b0;
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// advance the read pointer
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speculative_read_pointer_n = speculative_read_pointer_q + 1'b1;
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speculative_status_cnt--;
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end
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speculative_status_cnt_n = speculative_status_cnt;
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// when we flush evict the speculative stores
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if (flush_i) begin
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// reset all valid flags
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for (int unsigned i = 0; i < DEPTH_SPEC; i++)
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speculative_queue_n[i].valid = 1'b0;
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speculative_write_pointer_n = speculative_read_pointer_q;
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// also reset the status count
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speculative_status_cnt_n = 'b0;
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end
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end
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// ----------------------------------------
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// Commit Queue - Memory Interface
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// ----------------------------------------
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// we will never kill a request in the store buffer since we already know that the translation is valid
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// e.g.: a kill request will only be necessary if we are not sure if the requested memory address will result in a TLB fault
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assign req_port_o.kill_req = 1'b0;
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assign req_port_o.data_we = 1'b1; // we will always write in the store queue
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assign req_port_o.tag_valid = 1'b0;
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// those signals can directly be output to the memory
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assign req_port_o.address_index = commit_queue_q[commit_read_pointer_q].address[ariane_pkg::DCACHE_INDEX_WIDTH-1:0];
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// if we got a new request we already saved the tag from the previous cycle
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assign req_port_o.address_tag = commit_queue_q[commit_read_pointer_q].address[ariane_pkg::DCACHE_TAG_WIDTH +
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ariane_pkg::DCACHE_INDEX_WIDTH-1 :
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ariane_pkg::DCACHE_INDEX_WIDTH];
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assign req_port_o.data_wdata = commit_queue_q[commit_read_pointer_q].data;
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assign req_port_o.data_be = commit_queue_q[commit_read_pointer_q].be;
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assign req_port_o.data_size = commit_queue_q[commit_read_pointer_q].data_size;
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always_comb begin : store_if
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automatic logic [DEPTH_COMMIT:0] commit_status_cnt;
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commit_status_cnt = commit_status_cnt_q;
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commit_ready_o = (commit_status_cnt_q < DEPTH_COMMIT);
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// no store is pending if we don't have any element in the commit queue e.g.: it is empty
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no_st_pending_o = (commit_status_cnt_q == 0);
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// default assignments
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commit_read_pointer_n = commit_read_pointer_q;
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commit_write_pointer_n = commit_write_pointer_q;
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commit_queue_n = commit_queue_q;
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req_port_o.data_req = 1'b0;
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// there should be no commit when we are flushing
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// if the entry in the commit queue is valid and not speculative anymore we can issue this instruction
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if (commit_queue_q[commit_read_pointer_q].valid) begin
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req_port_o.data_req = 1'b1;
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if (req_port_i.data_gnt) begin
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// we can evict it from the commit buffer
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commit_queue_n[commit_read_pointer_q].valid = 1'b0;
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// advance the read_pointer
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commit_read_pointer_n = commit_read_pointer_q + 1'b1;
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commit_status_cnt--;
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end
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end
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// we ignore the rvalid signal for now as we assume that the store
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// happened if we got a grant
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// shift the store request from the speculative buffer to the non-speculative
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if (commit_i) begin
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commit_queue_n[commit_write_pointer_q] = speculative_queue_q[speculative_read_pointer_q];
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commit_write_pointer_n = commit_write_pointer_n + 1'b1;
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commit_status_cnt++;
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end
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commit_status_cnt_n = commit_status_cnt;
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end
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// ------------------
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// Address Checker
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// ------------------
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// The load should return the data stored by the most recent store to the
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// same physical address. The most direct way to implement this is to
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// maintain physical addresses in the store buffer.
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// Of course, there are other micro-architectural techniques to accomplish
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// the same thing: you can interlock and wait for the store buffer to
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// drain if the load VA matches any store VA modulo the page size (i.e.
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// bits 11:0). As a special case, it is correct to bypass if the full VA
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// matches, and no younger stores' VAs match in bits 11:0.
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//
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// checks if the requested load is in the store buffer
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// page offsets are virtually and physically the same
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always_comb begin : address_checker
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page_offset_matches_o = 1'b0;
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// check if the LSBs are identical and the entry is valid
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for (int unsigned i = 0; i < DEPTH_COMMIT; i++) begin
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// Check if the page offset matches and whether the entry is valid, for the commit queue
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if ((page_offset_i[11:3] == commit_queue_q[i].address[11:3]) && commit_queue_q[i].valid) begin
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page_offset_matches_o = 1'b1;
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break;
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end
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end
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for (int unsigned i = 0; i < DEPTH_SPEC; i++) begin
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// do the same for the speculative queue
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if ((page_offset_i[11:3] == speculative_queue_q[i].address[11:3]) && speculative_queue_q[i].valid) begin
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page_offset_matches_o = 1'b1;
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break;
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end
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end
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// or it matches with the entry we are currently putting into the queue
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if ((page_offset_i[11:3] == paddr_i[11:3]) && valid_without_flush_i) begin
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page_offset_matches_o = 1'b1;
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end
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end
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// registers
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always_ff @(posedge clk_i or negedge rst_ni) begin : p_spec
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if (~rst_ni) begin
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speculative_queue_q <= '{default: 0};
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speculative_read_pointer_q <= '0;
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speculative_write_pointer_q <= '0;
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speculative_status_cnt_q <= '0;
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end else begin
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speculative_queue_q <= speculative_queue_n;
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speculative_read_pointer_q <= speculative_read_pointer_n;
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speculative_write_pointer_q <= speculative_write_pointer_n;
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speculative_status_cnt_q <= speculative_status_cnt_n;
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end
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end
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// registers
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always_ff @(posedge clk_i or negedge rst_ni) begin : p_commit
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if (~rst_ni) begin
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commit_queue_q <= '{default: 0};
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commit_read_pointer_q <= '0;
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commit_write_pointer_q <= '0;
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commit_status_cnt_q <= '0;
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end else begin
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commit_queue_q <= commit_queue_n;
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commit_read_pointer_q <= commit_read_pointer_n;
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commit_write_pointer_q <= commit_write_pointer_n;
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commit_status_cnt_q <= commit_status_cnt_n;
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end
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end
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///////////////////////////////////////////////////////
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// assertions
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///////////////////////////////////////////////////////
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//pragma translate_off
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`ifndef VERILATOR
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// assert that commit is never set when we are flushing this would be counter intuitive
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// as flush and commit is decided in the same stage
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commit_and_flush: assert property (
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@(posedge clk_i) rst_ni && flush_i |-> !commit_i)
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else $error ("[Commit Queue] You are trying to commit and flush in the same cycle");
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speculative_buffer_overflow: assert property (
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@(posedge clk_i) rst_ni && (speculative_status_cnt_q == DEPTH_SPEC) |-> !valid_i)
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else $error ("[Speculative Queue] You are trying to push new data although the buffer is not ready");
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speculative_buffer_underflow: assert property (
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@(posedge clk_i) rst_ni && (speculative_status_cnt_q == 0) |-> !commit_i)
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else $error ("[Speculative Queue] You are committing although there are no stores to commit");
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commit_buffer_overflow: assert property (
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@(posedge clk_i) rst_ni && (commit_status_cnt_q == DEPTH_COMMIT) |-> !commit_i)
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else $error("[Commit Queue] You are trying to commit a store although the buffer is full");
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`endif
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//pragma translate_on
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endmodule
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