cva6/pd/synth/cva6_read.tcl
JeanRochCoulon b242c3f80b
pd: Add Synopsys DC synthesis target (#775)
* riscv_pkg.sv, cva6_imac_sv_config_pkg.sv: define FPU_EN as platform parameter

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

* scripts to make ASIC synthesis

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

* README.md: update synthesis and gate simulation descrption

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

* Update README.md

Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>

* Update pd/synth/Makefile

Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>

* Update pd/synth/cva6_read.tcl

Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>

* Update pd/synth/cva6_read.tcl

Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>

* Update pd/synth/cva6_synth.tcl

Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>

* Update pd/synth/scripts/dc_setup.tcl

Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>

* Update pd/synth/scripts/dc_setup_filenames.tcl

Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>

* Update pd/synth/scripts/gateAnalysis.py

Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>

* rename CVA6ConfigFpuen into CVA6ConfigFpuEn

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

* Revert "Update pd/synth/cva6_read.tcl"

This reverts commit 5e4433081d.

* cva6_read.tcl: read synthesis result

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

* define CACHE RAM INPUT_DELAY and OUTPUT_DELAY

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

* renale gateAnalysis.py

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

* fix input and output delays

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

* gate_analysis.py reformatted thanks to Black

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

* fix INPUT and OUTPUT DELAY setup

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
2021-12-13 19:17:43 +01:00

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479 B
Tcl

# Copyright 2021 Thales DIS design services SAS
#
# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
# You may obtain a copy of the License at https://solderpad.org/licenses/
#
# Original Author: Jean-Roch COULON (jean-roch.coulon@thalesgroup.com)
#
source -echo -verbose scripts/dc_setup.tcl
read_ddc ${DCRM_FINAL_DDC_OUTPUT_FILE}