mirror of
https://github.com/openhwgroup/cva6.git
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2df2fd8c8e
Use a PLIC which has been developed as part of the lowrisc project. It has been integrated into the Ariane SoC as a submodule pointing to a fork which has some (temporary) custom patches on top.
48 lines
1.7 KiB
Text
48 lines
1.7 KiB
Text
[submodule "src/axi_mem_if"]
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path = src/axi_mem_if
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url = https://github.com/pulp-platform/axi_mem_if.git
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[submodule "src/axi_node"]
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path = src/axi_node
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url = https://github.com/pulp-platform/axi_node.git
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[submodule "src/fpga-support"]
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path = src/fpga-support
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url = https://github.com/pulp-platform/fpga-support.git
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[submodule "src/common_cells"]
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path = src/common_cells
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url = https://github.com/pulp-platform/common_cells.git
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[submodule "src/axi"]
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path = src/axi
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url = https://github.com/pulp-platform/axi.git
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[submodule "src/register_interface"]
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path = src/register_interface
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url = https://github.com/pulp-platform/register_interface.git
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[submodule "fpga/src/apb_uart"]
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path = fpga/src/apb_uart
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url = https://github.com/pulp-platform/apb_uart.git
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[submodule "fpga/src/apb_node"]
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path = fpga/src/apb_node
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url = https://github.com/pulp-platform/apb_node.git
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[submodule "fpga/src/axi2apb"]
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path = fpga/src/axi2apb
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url = https://github.com/pulp-platform/axi2apb.git
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[submodule "fpga/src/axi_slice"]
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path = fpga/src/axi_slice
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url = https://github.com/pulp-platform/axi_slice.git
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[submodule "src/tech_cells_generic"]
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path = src/tech_cells_generic
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url = https://github.com/pulp-platform/tech_cells_generic.git
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[submodule "src/fpu"]
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path = src/fpu
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url = https://github.com/pulp-platform/fpnew.git
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[submodule "fpga/src/ariane-ethernet"]
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path = fpga/src/ariane-ethernet
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url = https://github.com/lowRISC/ariane-ethernet.git
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[submodule "src/axi_riscv_atomics"]
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path = src/axi_riscv_atomics
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url = https://github.com/pulp-platform/axi_riscv_atomics.git
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[submodule "src/riscv-dbg"]
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path = src/riscv-dbg
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url = https://github.com/pulp-platform/riscv-dbg.git
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[submodule "src/rv_plic"]
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path = src/rv_plic
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url = https://github.com/pulp-platform/rv_plic.git
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