mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-25 06:37:14 -04:00
07df142624
* : Fix PITON_ARIANE define issues * Fix write-back / cache read collision issue in serpent dcache. * Add separate bootrom / device tree for openpiton (hardcoded for 1x1 tile config at the moment). * Bootrom generation update (better compatibility with older python versions), new bootrom for OpenPiton+Ariane. * Fix assertion in icache. * Correct JTAG timing constraints. * Fix parameter type in fpga toplevel (fix #168). * Remove conflicting bootrom from fpga file list. * This flushs the branch predictors when entering exception handlers in order to avoid speculative fetches from virtual addresses (to be improved with PMAs). * Fix byte offset of IPIs in CLINT * Disable DCache flushes on fence for write-through cache (not needed in that case) * Fix blocking assignments in ff process. * Fix register access issue in debug mode, only affects A0 (fix #179). * Fix multiple driver issue in PLIC * Do not assume replicated data in serpent dcache when reading from an NC region. * Another byte offset fix in IPIs (CLINT) * Add AXI64 compliance switch to dcache_mem * Fix genesys 2 constraints * Map serpent atomic requests onto AXI atomic/exclusive transactions. * Cleanup of AXI memory plumbing, add separate AXI adapter module. * Remove unneeded interface signals, increase wbuffer #pending tx * Fix verilator compilation issues in AXI adapter. * Delete unnecessary constraint * Delete duplicate module instance * Update gitlab CI script * Small fixes to make riscv atomics work with serpent_axi_adapter. * Update travis and gitlab-ci scripts * Register b responses for better timing. * Remove fpu div submodule, update Makefile paths and src lists * Constant bits in haltsum reduction must be 1 (AND reduction). * Switch to DTM from riscv-dbg submodule * Further cleanup fixes in AXI/serpent atomics * Bump riscv-dbg version
19 lines
1.2 KiB
Tcl
19 lines
1.2 KiB
Tcl
## Common Ariane XDCs
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create_clock -period 100.000 -name tck -waveform {0.000 50.000} [get_ports tck]
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set_input_jitter tck 1.000
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# minimize routing delay
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set_input_delay -clock tck -clock_fall 5 [get_ports tdi ]
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set_input_delay -clock tck -clock_fall 5 [get_ports tms ]
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set_output_delay -clock tck 5 [get_ports tdo ]
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set_false_path -from [get_ports trst_n ]
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set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] -to [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] 20.000
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set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] -to [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 20.000
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set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] -to [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 20.000
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# set multicycle path on reset, on the FPGA we do not care about the reset anyway
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set_multicycle_path -from [get_pins i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]/C] 4
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set_multicycle_path -from [get_pins i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]/C] 3 -hold
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