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518 lines
20 KiB
Systemverilog
518 lines
20 KiB
Systemverilog
// Copyright 2018 ETH Zurich and University of Bologna.
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// Copyright and related rights are licensed under the Solderpad Hardware
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// License, Version 0.51 (the "License"); you may not use this file except in
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// compliance with the License. You may obtain a copy of the License at
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// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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// or agreed to in writing, software, hardware and materials distributed under
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// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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// CONDITIONS OF ANY KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations under the License.
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// Xilinx Peripehrals
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module ariane_peripherals #(
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parameter int AxiAddrWidth = -1,
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parameter int AxiDataWidth = -1,
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parameter int AxiIdWidth = -1,
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parameter int AxiUserWidth = 1,
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parameter bit InclUART = 1,
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parameter bit InclSPI = 0,
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parameter bit InclEthernet = 0,
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parameter bit InclGPIO = 0
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) (
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input logic clk_i , // Clock
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input logic rst_ni , // Asynchronous reset active low
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AXI_BUS.Slave plic ,
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AXI_BUS.Slave uart ,
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AXI_BUS.Slave spi ,
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AXI_BUS.Slave ethernet ,
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output logic [1:0] irq_o ,
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// UART
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input logic rx_i ,
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output logic tx_o ,
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// Ethernet
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input wire eth_txck ,
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input wire eth_rxck ,
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input wire eth_rxctl ,
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input wire [3:0] eth_rxd ,
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output wire eth_rst_n ,
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output wire eth_tx_en ,
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output wire [3:0] eth_txd ,
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inout wire phy_mdio ,
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output logic eth_mdc ,
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// MDIO Interface
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inout mdio ,
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output mdc ,
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// SPI
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output logic spi_clk_o ,
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output logic spi_mosi ,
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input logic spi_miso ,
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output logic spi_ss
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);
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// ---------------
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// 1. PLIC
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// ---------------
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logic [ariane_soc::NumSources-1:0] irq_sources;
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REG_BUS #(
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.ADDR_WIDTH ( 32 ),
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.DATA_WIDTH ( 32 )
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) reg_bus (clk_i);
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logic plic_penable;
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logic plic_pwrite;
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logic [31:0] plic_paddr;
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logic plic_psel;
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logic [31:0] plic_pwdata;
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logic [31:0] plic_prdata;
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logic plic_pready;
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logic plic_pslverr;
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axi2apb_64_32 #(
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.AXI4_ADDRESS_WIDTH ( AxiAddrWidth ),
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.AXI4_RDATA_WIDTH ( AxiDataWidth ),
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.AXI4_WDATA_WIDTH ( AxiDataWidth ),
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.AXI4_ID_WIDTH ( AxiIdWidth ),
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.AXI4_USER_WIDTH ( AxiUserWidth ),
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.BUFF_DEPTH_SLAVE ( 2 ),
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.APB_ADDR_WIDTH ( 32 )
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) i_axi2apb_64_32_plic (
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.ACLK ( clk_i ),
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.ARESETn ( rst_ni ),
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.test_en_i ( 1'b0 ),
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.AWID_i ( plic.aw_id ),
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.AWADDR_i ( plic.aw_addr ),
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.AWLEN_i ( plic.aw_len ),
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.AWSIZE_i ( plic.aw_size ),
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.AWBURST_i ( plic.aw_burst ),
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.AWLOCK_i ( plic.aw_lock ),
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.AWCACHE_i ( plic.aw_cache ),
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.AWPROT_i ( plic.aw_prot ),
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.AWREGION_i( plic.aw_region ),
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.AWUSER_i ( plic.aw_user ),
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.AWQOS_i ( plic.aw_qos ),
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.AWVALID_i ( plic.aw_valid ),
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.AWREADY_o ( plic.aw_ready ),
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.WDATA_i ( plic.w_data ),
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.WSTRB_i ( plic.w_strb ),
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.WLAST_i ( plic.w_last ),
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.WUSER_i ( plic.w_user ),
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.WVALID_i ( plic.w_valid ),
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.WREADY_o ( plic.w_ready ),
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.BID_o ( plic.b_id ),
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.BRESP_o ( plic.b_resp ),
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.BVALID_o ( plic.b_valid ),
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.BUSER_o ( plic.b_user ),
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.BREADY_i ( plic.b_ready ),
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.ARID_i ( plic.ar_id ),
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.ARADDR_i ( plic.ar_addr ),
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.ARLEN_i ( plic.ar_len ),
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.ARSIZE_i ( plic.ar_size ),
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.ARBURST_i ( plic.ar_burst ),
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.ARLOCK_i ( plic.ar_lock ),
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.ARCACHE_i ( plic.ar_cache ),
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.ARPROT_i ( plic.ar_prot ),
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.ARREGION_i( plic.ar_region ),
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.ARUSER_i ( plic.ar_user ),
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.ARQOS_i ( plic.ar_qos ),
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.ARVALID_i ( plic.ar_valid ),
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.ARREADY_o ( plic.ar_ready ),
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.RID_o ( plic.r_id ),
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.RDATA_o ( plic.r_data ),
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.RRESP_o ( plic.r_resp ),
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.RLAST_o ( plic.r_last ),
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.RUSER_o ( plic.r_user ),
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.RVALID_o ( plic.r_valid ),
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.RREADY_i ( plic.r_ready ),
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.PENABLE ( plic_penable ),
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.PWRITE ( plic_pwrite ),
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.PADDR ( plic_paddr ),
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.PSEL ( plic_psel ),
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.PWDATA ( plic_pwdata ),
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.PRDATA ( plic_prdata ),
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.PREADY ( plic_pready ),
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.PSLVERR ( plic_pslverr )
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);
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apb_to_reg i_apb_to_reg (
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.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
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.penable_i ( plic_penable ),
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.pwrite_i ( plic_pwrite ),
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.paddr_i ( plic_paddr ),
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.psel_i ( plic_psel ),
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.pwdata_i ( plic_pwdata ),
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.prdata_o ( plic_prdata ),
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.pready_o ( plic_pready ),
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.pslverr_o ( plic_pslverr ),
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.reg_o ( reg_bus )
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);
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reg_intf::reg_intf_resp_d32 plic_resp;
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reg_intf::reg_intf_req_a32_d32 plic_req;
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assign plic_req.addr = reg_bus.addr;
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assign plic_req.write = reg_bus.write;
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assign plic_req.wdata = reg_bus.wdata;
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assign plic_req.wstrb = reg_bus.wstrb;
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assign plic_req.valid = reg_bus.valid;
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assign reg_bus.rdata = plic_resp.rdata;
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assign reg_bus.error = plic_resp.error;
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assign reg_bus.ready = plic_resp.ready;
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plic_top #(
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.N_SOURCE ( ariane_soc::NumSources ),
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.N_TARGET ( ariane_soc::NumTargets ),
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.MAX_PRIO ( ariane_soc::MaxPriority )
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) i_plic (
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.clk_i,
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.rst_ni,
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.req_i ( plic_req ),
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.resp_o ( plic_resp ),
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.le_i ( '0 ), // 0:level 1:edge
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.irq_sources_i ( irq_sources ),
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.eip_targets_o ( irq_o )
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);
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// ---------------
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// 2. UART
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// ---------------
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logic uart_penable;
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logic uart_pwrite;
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logic [31:0] uart_paddr;
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logic uart_psel;
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logic [31:0] uart_pwdata;
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logic [31:0] uart_prdata;
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logic uart_pready;
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logic uart_pslverr;
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axi2apb_64_32 #(
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.AXI4_ADDRESS_WIDTH ( AxiAddrWidth ),
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.AXI4_RDATA_WIDTH ( AxiDataWidth ),
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.AXI4_WDATA_WIDTH ( AxiDataWidth ),
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.AXI4_ID_WIDTH ( AxiIdWidth ),
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.AXI4_USER_WIDTH ( AxiUserWidth ),
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.BUFF_DEPTH_SLAVE ( 2 ),
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.APB_ADDR_WIDTH ( 32 )
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) i_axi2apb_64_32_uart (
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.ACLK ( clk_i ),
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.ARESETn ( rst_ni ),
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.test_en_i ( 1'b0 ),
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.AWID_i ( uart.aw_id ),
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.AWADDR_i ( uart.aw_addr ),
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.AWLEN_i ( uart.aw_len ),
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.AWSIZE_i ( uart.aw_size ),
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.AWBURST_i ( uart.aw_burst ),
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.AWLOCK_i ( uart.aw_lock ),
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.AWCACHE_i ( uart.aw_cache ),
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.AWPROT_i ( uart.aw_prot ),
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.AWREGION_i( uart.aw_region ),
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.AWUSER_i ( uart.aw_user ),
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.AWQOS_i ( uart.aw_qos ),
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.AWVALID_i ( uart.aw_valid ),
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.AWREADY_o ( uart.aw_ready ),
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.WDATA_i ( uart.w_data ),
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.WSTRB_i ( uart.w_strb ),
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.WLAST_i ( uart.w_last ),
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.WUSER_i ( uart.w_user ),
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.WVALID_i ( uart.w_valid ),
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.WREADY_o ( uart.w_ready ),
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.BID_o ( uart.b_id ),
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.BRESP_o ( uart.b_resp ),
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.BVALID_o ( uart.b_valid ),
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.BUSER_o ( uart.b_user ),
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.BREADY_i ( uart.b_ready ),
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.ARID_i ( uart.ar_id ),
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.ARADDR_i ( uart.ar_addr ),
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.ARLEN_i ( uart.ar_len ),
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.ARSIZE_i ( uart.ar_size ),
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.ARBURST_i ( uart.ar_burst ),
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.ARLOCK_i ( uart.ar_lock ),
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.ARCACHE_i ( uart.ar_cache ),
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.ARPROT_i ( uart.ar_prot ),
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.ARREGION_i( uart.ar_region ),
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.ARUSER_i ( uart.ar_user ),
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.ARQOS_i ( uart.ar_qos ),
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.ARVALID_i ( uart.ar_valid ),
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.ARREADY_o ( uart.ar_ready ),
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.RID_o ( uart.r_id ),
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.RDATA_o ( uart.r_data ),
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.RRESP_o ( uart.r_resp ),
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.RLAST_o ( uart.r_last ),
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.RUSER_o ( uart.r_user ),
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.RVALID_o ( uart.r_valid ),
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.RREADY_i ( uart.r_ready ),
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.PENABLE ( uart_penable ),
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.PWRITE ( uart_pwrite ),
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.PADDR ( uart_paddr ),
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.PSEL ( uart_psel ),
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.PWDATA ( uart_pwdata ),
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.PRDATA ( uart_prdata ),
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.PREADY ( uart_pready ),
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.PSLVERR ( uart_pslverr )
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);
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if (InclUART) begin : gen_uart
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apb_uart i_apb_uart (
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.CLK ( clk_i ),
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.RSTN ( rst_ni ),
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.PSEL ( uart_psel ),
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.PENABLE ( uart_penable ),
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.PWRITE ( uart_pwrite ),
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.PADDR ( uart_paddr[4:2] ),
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.PWDATA ( uart_pwdata ),
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.PRDATA ( uart_prdata ),
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.PREADY ( uart_pready ),
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.PSLVERR ( uart_pslverr ),
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.INT ( irq_sources[0] ),
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.OUT1N ( ), // keep open
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.OUT2N ( ), // keep open
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.RTSN ( ), // no flow control
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.DTRN ( ), // no flow control
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.CTSN ( 1'b0 ),
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.DSRN ( 1'b0 ),
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.DCDN ( 1'b0 ),
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.RIN ( 1'b0 ),
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.SIN ( rx_i ),
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.SOUT ( tx_o )
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);
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end else begin
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assign irq_sources[0] = 1'b0;
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/* pragma translate_off */
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`ifndef VERILATOR
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mock_uart i_mock_uart (
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.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
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.penable_i ( uart_penable ),
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.pwrite_i ( uart_pwrite ),
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.paddr_i ( uart_paddr ),
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.psel_i ( uart_psel ),
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.pwdata_i ( uart_pwdata ),
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.prdata_o ( uart_prdata ),
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.pready_o ( uart_pready ),
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.pslverr_o ( uart_pslverr )
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);
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`endif
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/* pragma translate_on */
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end
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// ---------------
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// 3. SPI
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// ---------------
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if (InclSPI) begin : gen_spi
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logic [31:0] s_axi_spi_awaddr;
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logic [7:0] s_axi_spi_awlen;
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logic [2:0] s_axi_spi_awsize;
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logic [1:0] s_axi_spi_awburst;
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logic [0:0] s_axi_spi_awlock;
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logic [3:0] s_axi_spi_awcache;
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logic [2:0] s_axi_spi_awprot;
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logic [3:0] s_axi_spi_awregion;
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logic [3:0] s_axi_spi_awqos;
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logic s_axi_spi_awvalid;
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logic s_axi_spi_awready;
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logic [31:0] s_axi_spi_wdata;
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logic [3:0] s_axi_spi_wstrb;
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logic s_axi_spi_wlast;
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logic s_axi_spi_wvalid;
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logic s_axi_spi_wready;
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logic [1:0] s_axi_spi_bresp;
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logic s_axi_spi_bvalid;
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logic s_axi_spi_bready;
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logic [31:0] s_axi_spi_araddr;
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logic [7:0] s_axi_spi_arlen;
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logic [2:0] s_axi_spi_arsize;
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logic [1:0] s_axi_spi_arburst;
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logic [0:0] s_axi_spi_arlock;
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logic [3:0] s_axi_spi_arcache;
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logic [2:0] s_axi_spi_arprot;
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logic [3:0] s_axi_spi_arregion;
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logic [3:0] s_axi_spi_arqos;
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logic s_axi_spi_arvalid;
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logic s_axi_spi_arready;
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logic [31:0] s_axi_spi_rdata;
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logic [1:0] s_axi_spi_rresp;
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logic s_axi_spi_rlast;
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logic s_axi_spi_rvalid;
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logic s_axi_spi_rready;
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xlnx_axi_clock_converter i_xlnx_axi_clock_converter_spi (
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.s_axi_aclk ( clk_i ),
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.s_axi_aresetn ( rst_ni ),
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.s_axi_awid ( spi.aw_id ),
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.s_axi_awaddr ( spi.aw_addr[31:0] ),
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.s_axi_awlen ( spi.aw_len ),
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.s_axi_awsize ( spi.aw_size ),
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.s_axi_awburst ( spi.aw_burst ),
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.s_axi_awlock ( spi.aw_lock ),
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.s_axi_awcache ( spi.aw_cache ),
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.s_axi_awprot ( spi.aw_prot ),
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.s_axi_awregion ( spi.aw_region ),
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.s_axi_awqos ( spi.aw_qos ),
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.s_axi_awvalid ( spi.aw_valid ),
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.s_axi_awready ( spi.aw_ready ),
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.s_axi_wdata ( spi.w_data ),
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.s_axi_wstrb ( spi.w_strb ),
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.s_axi_wlast ( spi.w_last ),
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.s_axi_wvalid ( spi.w_valid ),
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.s_axi_wready ( spi.w_ready ),
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.s_axi_bid ( spi.b_id ),
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.s_axi_bresp ( spi.b_resp ),
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.s_axi_bvalid ( spi.b_valid ),
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.s_axi_bready ( spi.b_ready ),
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.s_axi_arid ( spi.ar_id ),
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.s_axi_araddr ( spi.ar_addr[31:0] ),
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.s_axi_arlen ( spi.ar_len ),
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.s_axi_arsize ( spi.ar_size ),
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.s_axi_arburst ( spi.ar_burst ),
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.s_axi_arlock ( spi.ar_lock ),
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.s_axi_arcache ( spi.ar_cache ),
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.s_axi_arprot ( spi.ar_prot ),
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.s_axi_arregion ( spi.ar_region ),
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.s_axi_arqos ( spi.ar_qos ),
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.s_axi_arvalid ( spi.ar_valid ),
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.s_axi_arready ( spi.ar_ready ),
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.s_axi_rid ( spi.r_id ),
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.s_axi_rdata ( spi.r_data ),
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.s_axi_rresp ( spi.r_resp ),
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.s_axi_rlast ( spi.r_last ),
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.s_axi_rvalid ( spi.r_valid ),
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.s_axi_rready ( spi.r_ready ),
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.m_axi_awaddr ( s_axi_spi_awaddr ),
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.m_axi_awlen ( s_axi_spi_awlen ),
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.m_axi_awsize ( s_axi_spi_awsize ),
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.m_axi_awburst ( s_axi_spi_awburst ),
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.m_axi_awlock ( s_axi_spi_awlock ),
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.m_axi_awcache ( s_axi_spi_awcache ),
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.m_axi_awprot ( s_axi_spi_awprot ),
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.m_axi_awregion ( s_axi_spi_awregion ),
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.m_axi_awqos ( s_axi_spi_awqos ),
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.m_axi_awvalid ( s_axi_spi_awvalid ),
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.m_axi_awready ( s_axi_spi_awready ),
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.m_axi_wdata ( s_axi_spi_wdata ),
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.m_axi_wstrb ( s_axi_spi_wstrb ),
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.m_axi_wlast ( s_axi_spi_wlast ),
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.m_axi_wvalid ( s_axi_spi_wvalid ),
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.m_axi_wready ( s_axi_spi_wready ),
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.m_axi_bresp ( s_axi_spi_bresp ),
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.m_axi_bvalid ( s_axi_spi_bvalid ),
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.m_axi_bready ( s_axi_spi_bready ),
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.m_axi_araddr ( s_axi_spi_araddr ),
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.m_axi_arlen ( s_axi_spi_arlen ),
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.m_axi_arsize ( s_axi_spi_arsize ),
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.m_axi_arburst ( s_axi_spi_arburst ),
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.m_axi_arlock ( s_axi_spi_arlock ),
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.m_axi_arcache ( s_axi_spi_arcache ),
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.m_axi_arprot ( s_axi_spi_arprot ),
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.m_axi_arregion ( s_axi_spi_arregion ),
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.m_axi_arqos ( s_axi_spi_arqos ),
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.m_axi_arvalid ( s_axi_spi_arvalid ),
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.m_axi_arready ( s_axi_spi_arready ),
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.m_axi_rdata ( s_axi_spi_rdata ),
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.m_axi_rresp ( s_axi_spi_rresp ),
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.m_axi_rlast ( s_axi_spi_rlast ),
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.m_axi_rvalid ( s_axi_spi_rvalid ),
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.m_axi_rready ( s_axi_spi_rready )
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);
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|
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xlnx_axi_quad_spi i_xlnx_axi_quad_spi (
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.ext_spi_clk ( clk_i ),
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.s_axi4_aclk ( clk_i ),
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.s_axi4_aresetn ( rst_ni ),
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.s_axi4_awaddr ( s_axi_spi_awaddr[23:0] ),
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.s_axi4_awlen ( s_axi_spi_awlen ),
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.s_axi4_awsize ( s_axi_spi_awsize ),
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.s_axi4_awburst ( s_axi_spi_awburst ),
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.s_axi4_awlock ( s_axi_spi_awlock ),
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|
.s_axi4_awcache ( s_axi_spi_awcache ),
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|
.s_axi4_awprot ( s_axi_spi_awprot ),
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.s_axi4_awvalid ( s_axi_spi_awvalid ),
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|
.s_axi4_awready ( s_axi_spi_awready ),
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|
.s_axi4_wdata ( s_axi_spi_wdata ),
|
|
.s_axi4_wstrb ( s_axi_spi_wstrb ),
|
|
.s_axi4_wlast ( s_axi_spi_wlast ),
|
|
.s_axi4_wvalid ( s_axi_spi_wvalid ),
|
|
.s_axi4_wready ( s_axi_spi_wready ),
|
|
.s_axi4_bresp ( s_axi_spi_bresp ),
|
|
.s_axi4_bvalid ( s_axi_spi_bvalid ),
|
|
.s_axi4_bready ( s_axi_spi_bready ),
|
|
.s_axi4_araddr ( s_axi_spi_araddr[23:0] ),
|
|
.s_axi4_arlen ( s_axi_spi_arlen ),
|
|
.s_axi4_arsize ( s_axi_spi_arsize ),
|
|
.s_axi4_arburst ( s_axi_spi_arburst ),
|
|
.s_axi4_arlock ( s_axi_spi_arlock ),
|
|
.s_axi4_arcache ( s_axi_spi_arcache ),
|
|
.s_axi4_arprot ( s_axi_spi_arprot ),
|
|
.s_axi4_arvalid ( s_axi_spi_arvalid ),
|
|
.s_axi4_arready ( s_axi_spi_arready ),
|
|
.s_axi4_rdata ( s_axi_spi_rdata ),
|
|
.s_axi4_rresp ( s_axi_spi_rresp ),
|
|
.s_axi4_rlast ( s_axi_spi_rlast ),
|
|
.s_axi4_rvalid ( s_axi_spi_rvalid ),
|
|
.s_axi4_rready ( s_axi_spi_rready ),
|
|
|
|
.io0_i ( '0 ),
|
|
.io0_o ( spi_mosi ),
|
|
.io0_t ( '0 ),
|
|
.io1_i ( spi_miso ),
|
|
.io1_o ( ),
|
|
.io1_t ( '0 ),
|
|
.ss_i ( '0 ),
|
|
.ss_o ( spi_ss ),
|
|
.ss_t ( '0 ),
|
|
.sck_o ( spi_clk_o ),
|
|
.sck_i ( '0 ),
|
|
.sck_t ( ),
|
|
.ip2intc_irpt ( irq_sources[1] )
|
|
// .ip2intc_irpt ( irq_sources[1] )
|
|
);
|
|
// assign irq_sources [1] = 1'b0;
|
|
end else begin
|
|
assign spi_clk_o = 1'b0;
|
|
assign spi_mosi = 1'b0;
|
|
assign spi_ss = 1'b0;
|
|
|
|
assign irq_sources [1] = 1'b0;
|
|
assign spi.aw_ready = 1'b1;
|
|
assign spi.ar_ready = 1'b1;
|
|
assign spi.w_ready = 1'b1;
|
|
|
|
assign spi.b_valid = spi.aw_valid;
|
|
assign spi.b_id = spi.aw_id;
|
|
assign spi.b_resp = axi_pkg::RESP_SLVERR;
|
|
assign spi.b_user = '0;
|
|
|
|
assign spi.r_valid = spi.ar_valid;
|
|
assign spi.r_resp = axi_pkg::RESP_SLVERR;
|
|
assign spi.r_data = 'hdeadbeef;
|
|
assign spi.r_last = 1'b1;
|
|
end
|
|
|
|
|
|
// ---------------
|
|
// 4. Ethernet
|
|
// ---------------
|
|
if (0)
|
|
begin
|
|
end
|
|
else
|
|
begin
|
|
assign irq_sources [2] = 1'b0;
|
|
assign ethernet.aw_ready = 1'b1;
|
|
assign ethernet.ar_ready = 1'b1;
|
|
assign ethernet.w_ready = 1'b1;
|
|
|
|
assign ethernet.b_valid = ethernet.aw_valid;
|
|
assign ethernet.b_id = ethernet.aw_id;
|
|
assign ethernet.b_resp = axi_pkg::RESP_SLVERR;
|
|
assign ethernet.b_user = '0;
|
|
|
|
assign ethernet.r_valid = ethernet.ar_valid;
|
|
assign ethernet.r_resp = axi_pkg::RESP_SLVERR;
|
|
assign ethernet.r_data = 'hdeadbeef;
|
|
assign ethernet.r_last = 1'b1;
|
|
end
|
|
endmodule
|