mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-22 21:27:10 -04:00
a5f3184a65
* Add spike isa sim * Fix AMO problem in verilator * 🎨 Tidy up FPU wrapper * Bump axi_exclusive submodule * Refactor serpent AXI adapter, bump dbg and atomics submodules, add separate bootrom for linux on OpenPiton (#190) * Refactor serpent AXI adapter * Disable FPU in OpenPiton by default * Bump dbg and atomics submodules * Fix cache testbenches (interface change) * FPGA bootrom changes for OpenPiton SDHC * Introduce two bootroms, one for baremetal apps (pitonstream), and one for linux boot from SD * Testing barrier-based synchronisation instead of CLINT-based * This bootrom works for 2 core on g2 and if you change MAX_HARTS to 4, then 4 cores on vc707 * Add MAX_HARTS switch to makefile * Fix gitlab CI * Revert standard FPGA bootrom * Update Flist * Make UART_FREQ a parameter * Fix typo in tb.list and an error in define switch in ariane_pkg * Copy over SD-driver in bootloader from @leon575777642 * Fix compilation issues of bootrom * Change signal name in serpent periph portlist * Correct generate statement in serpent dcache memory * Add Piton SD Controller, FPGA fixes * Fix race condition in dcache misshandler * Add tandem spike to Make flow * Remove OpenPiton SD Card controller again
95 lines
No EOL
2.3 KiB
C++
95 lines
No EOL
2.3 KiB
C++
// See LICENSE for license details.
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#ifndef _RISCV_SPIKE_H
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#define _RISCV_SPIKE_H
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#include "processor.h"
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#include "devices.h"
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#include "debug_module.h"
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#include "simif.h"
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#include <fesvr/htif.h>
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#include <fesvr/context.h>
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#include <vector>
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#include <string>
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#include <memory>
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#include <thread>
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class mmu_t;
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class remote_bitbang_t;
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typedef struct
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{
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char priv;
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uint64_t pc;
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char is_fp;
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char rd;
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uint64_t data;
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uint32_t instr;
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char was_exception;
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} commit_log_t;
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// this class encapsulates the processors and memory in a RISC-V machine.
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class sim_spike_t : public simif_t
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{
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public:
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sim_spike_t(const char* isa, size_t _nprocs,
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std::vector<std::pair<reg_t, mem_t*>> mems,
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const std::vector<std::string>& args);
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~sim_spike_t();
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int init_sim();
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void producer_thread();
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void clint_tick();
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commit_log_t tick(size_t n); // step through simulation
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void set_debug(bool value);
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void set_log(bool value);
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void set_histogram(bool value);
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void set_procs_debug(bool value);
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void set_dtb_enabled(bool value) {
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this->dtb_enabled = value;
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}
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void set_remote_bitbang(remote_bitbang_t* remote_bitbang) {
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this->remote_bitbang = remote_bitbang;
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}
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const char* get_dts() { return dts.c_str(); }
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processor_t* get_core(size_t i) { return procs.at(i); }
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unsigned nprocs() const { return procs.size(); }
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private:
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std::vector<std::pair<reg_t, mem_t*>> mems;
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mmu_t* debug_mmu; // debug port into main memory
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std::vector<processor_t*> procs;
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reg_t start_pc;
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std::string dts;
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std::unique_ptr<rom_device_t> boot_rom;
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std::unique_ptr<clint_t> clint;
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std::unique_ptr<uart_t> uart;
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bus_t bus;
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std::thread t1;
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processor_t* get_core(const std::string& i);
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static const size_t INTERLEAVE = 5000;
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static const size_t INSNS_PER_RTC_TICK = 100; // 10 MHz clock for 1 BIPS core
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static const size_t CPU_HZ = 1000000000; // 1GHz CPU
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size_t current_step;
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size_t current_proc;
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bool debug;
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bool log;
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bool histogram_enabled; // provide a histogram of PCs
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bool dtb_enabled;
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remote_bitbang_t* remote_bitbang;
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// memory-mapped I/O routines
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char* addr_to_mem(reg_t addr);
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bool mmio_load(reg_t addr, size_t len, uint8_t* bytes);
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bool mmio_store(reg_t addr, size_t len, const uint8_t* bytes);
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void proc_reset(unsigned id) {};
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void make_bootrom();
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public:
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};
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#endif |