mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-24 14:17:16 -04:00
a5f3184a65
* Add spike isa sim * Fix AMO problem in verilator * 🎨 Tidy up FPU wrapper * Bump axi_exclusive submodule * Refactor serpent AXI adapter, bump dbg and atomics submodules, add separate bootrom for linux on OpenPiton (#190) * Refactor serpent AXI adapter * Disable FPU in OpenPiton by default * Bump dbg and atomics submodules * Fix cache testbenches (interface change) * FPGA bootrom changes for OpenPiton SDHC * Introduce two bootroms, one for baremetal apps (pitonstream), and one for linux boot from SD * Testing barrier-based synchronisation instead of CLINT-based * This bootrom works for 2 core on g2 and if you change MAX_HARTS to 4, then 4 cores on vc707 * Add MAX_HARTS switch to makefile * Fix gitlab CI * Revert standard FPGA bootrom * Update Flist * Make UART_FREQ a parameter * Fix typo in tb.list and an error in define switch in ariane_pkg * Copy over SD-driver in bootloader from @leon575777642 * Fix compilation issues of bootrom * Change signal name in serpent periph portlist * Correct generate statement in serpent dcache memory * Add Piton SD Controller, FPGA fixes * Fix race condition in dcache misshandler * Add tandem spike to Make flow * Remove OpenPiton SD Card controller again
72 lines
2.7 KiB
ArmAsm
Executable file
72 lines
2.7 KiB
ArmAsm
Executable file
// See LICENSE.SiFive for license details.
|
|
|
|
#include "riscv/encoding.h"
|
|
#include "riscv/debug_rom_defines.h"
|
|
|
|
.option norvc
|
|
.global entry
|
|
.global exception
|
|
|
|
// Entry location on ebreak, Halt, or Breakpoint
|
|
// It is the same for all harts. They branch when
|
|
// their GO or RESUME bit is set.
|
|
|
|
entry:
|
|
jal zero, _entry
|
|
resume:
|
|
jal zero, _resume
|
|
exception:
|
|
jal zero, _exception
|
|
|
|
_entry:
|
|
// This fence is required because the execution may have written something
|
|
// into the Abstract Data or Program Buffer registers.
|
|
fence
|
|
csrw CSR_DSCRATCH, s0 // Save s0 to allow signaling MHARTID
|
|
|
|
// We continue to let the hart know that we are halted in order that
|
|
// a DM which was reset is still made aware that a hart is halted.
|
|
// We keep checking both whether there is something the debugger wants
|
|
// us to do, or whether we should resume.
|
|
entry_loop:
|
|
csrr s0, CSR_MHARTID
|
|
sw s0, DEBUG_ROM_HALTED(zero)
|
|
lbu s0, DEBUG_ROM_FLAGS(s0) // 1 byte flag per hart. Only one hart advances here.
|
|
andi s0, s0, (1 << DEBUG_ROM_FLAG_GO)
|
|
bnez s0, going
|
|
csrr s0, CSR_MHARTID
|
|
lbu s0, DEBUG_ROM_FLAGS(s0) // multiple harts can resume here
|
|
andi s0, s0, (1 << DEBUG_ROM_FLAG_RESUME)
|
|
bnez s0, resume
|
|
jal zero, entry_loop
|
|
|
|
_exception:
|
|
sw zero, DEBUG_ROM_EXCEPTION(zero) // Let debug module know you got an exception.
|
|
ebreak
|
|
|
|
going:
|
|
csrr s0, CSR_DSCRATCH // Restore s0 here
|
|
sw zero, DEBUG_ROM_GOING(zero) // When debug module sees this write, the GO flag is reset.
|
|
fence
|
|
fence.i
|
|
jalr zero, zero, %lo(whereto) // Debug module will put different instructions and data in the RAM,
|
|
// so we use fence and fence.i for safety. (rocket-chip doesn't have this
|
|
// because jalr is special there)
|
|
|
|
_resume:
|
|
csrr s0, CSR_MHARTID
|
|
sw s0, DEBUG_ROM_RESUMING(zero) // When Debug Module sees this write, the RESUME flag is reset.
|
|
csrr s0, CSR_DSCRATCH // Restore s0
|
|
dret
|
|
|
|
// END OF ACTUAL "ROM" CONTENTS. BELOW IS JUST FOR LINKER SCRIPT.
|
|
|
|
.section .whereto
|
|
whereto:
|
|
nop
|
|
// Variable "ROM" This is : jal x0 abstract, jal x0 program_buffer,
|
|
// or jal x0 resume, as desired.
|
|
// Debug Module state machine tracks what is 'desired'.
|
|
// We don't need/want to use jalr here because all of the
|
|
// Variable ROM contents are set by
|
|
// Debug Module before setting the OK_GO byte.
|