mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-24 22:27:10 -04:00
a5f3184a65
* Add spike isa sim * Fix AMO problem in verilator * 🎨 Tidy up FPU wrapper * Bump axi_exclusive submodule * Refactor serpent AXI adapter, bump dbg and atomics submodules, add separate bootrom for linux on OpenPiton (#190) * Refactor serpent AXI adapter * Disable FPU in OpenPiton by default * Bump dbg and atomics submodules * Fix cache testbenches (interface change) * FPGA bootrom changes for OpenPiton SDHC * Introduce two bootroms, one for baremetal apps (pitonstream), and one for linux boot from SD * Testing barrier-based synchronisation instead of CLINT-based * This bootrom works for 2 core on g2 and if you change MAX_HARTS to 4, then 4 cores on vc707 * Add MAX_HARTS switch to makefile * Fix gitlab CI * Revert standard FPGA bootrom * Update Flist * Make UART_FREQ a parameter * Fix typo in tb.list and an error in define switch in ariane_pkg * Copy over SD-driver in bootloader from @leon575777642 * Fix compilation issues of bootrom * Change signal name in serpent periph portlist * Correct generate statement in serpent dcache memory * Add Piton SD Controller, FPGA fixes * Fix race condition in dcache misshandler * Add tandem spike to Make flow * Remove OpenPiton SD Card controller again
37 lines
1.2 KiB
C
Executable file
37 lines
1.2 KiB
C
Executable file
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#include <stdbool.h>
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#include <stdint.h>
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#include "platform.h"
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#include "internals.h"
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#include "specialize.h"
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#include "softfloat.h"
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uint_fast16_t f128_classify( float128_t a )
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{
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union ui128_f128 uA;
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uint_fast64_t uiA64, uiA0;
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uA.f = a;
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uiA64 = uA.ui.v64;
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uiA0 = uA.ui.v0;
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uint_fast16_t infOrNaN = expF128UI64( uiA64 ) == 0x7FFF;
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uint_fast16_t subnormalOrZero = expF128UI64( uiA64 ) == 0;
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bool sign = signF128UI64( uiA64 );
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bool fracZero = fracF128UI64( uiA64 ) == 0 && uiA0 == 0;
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bool isNaN = isNaNF128UI( uiA64, uiA0 );
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bool isSNaN = softfloat_isSigNaNF128UI( uiA64, uiA0 );
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return
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( sign && infOrNaN && fracZero ) << 0 |
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( sign && !infOrNaN && !subnormalOrZero ) << 1 |
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( sign && subnormalOrZero && !fracZero ) << 2 |
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( sign && subnormalOrZero && fracZero ) << 3 |
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( !sign && infOrNaN && fracZero ) << 7 |
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( !sign && !infOrNaN && !subnormalOrZero ) << 6 |
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( !sign && subnormalOrZero && !fracZero ) << 5 |
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( !sign && subnormalOrZero && fracZero ) << 4 |
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( isNaN && isSNaN ) << 8 |
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( isNaN && !isSNaN ) << 9;
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}
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