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ad223cfd9f
* Clean-up naming to distinguish OP from GP Ariane * Rename wb to wt in hidden CI files * Fix verilator install script
42 lines
1.5 KiB
Makefile
Executable file
42 lines
1.5 KiB
Makefile
Executable file
# Copyright 2018 ETH Zurich and University of Bologna.
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# Copyright and related rights are licensed under the Solderpad Hardware
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# License, Version 0.51 (the "License"); you may not use this file except in
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# compliance with the License. You may obtain a copy of the License at
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# http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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# or agreed to in writing, software, hardware and materials distributed under
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# this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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# CONDITIONS OF ANY KIND, either express or implied. See the License for the
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# specific language governing permissions and limitations under the License.
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#
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# Author: Michael Schaffner <schaffner@iis.ee.ethz.ch>, ETH Zurich
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# Date: 15.08.2018
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# Description: Makefile for the icache testbench.
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library ?= work
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toplevel ?= tb
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src-list := tb.list
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src := $(shell xargs printf '\n%s' < $(src-list) | cut -b 1-)
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compile_flag += +cover+/dut -incr -64 -nologo
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sim_opts += -64 -coverage -classdebug -voptargs="+acc"
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questa_version ?= ${QUESTASIM_VERSION}
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incdir += ../common/
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build: clean
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vlib${questa_version} $(library)
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vlog${questa_version} -work $(library) -pedanticerrors $(src) $(compile_flag) +incdir+$(incdir)
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touch $(library)/.build
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# this starts modelsim with gui
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sim: build
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vsim${questa_version} -lib $(library) $(toplevel) -do "do wave.do" $(sim_opts)
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# batch mode without gui
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simc: build
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vsim${questa_version} -lib $(library) $(toplevel) -c -do "run -all; exit" $(sim_opts)
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clean:
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rm -rf $(library)
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.PHONY: clean simc sim build
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