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Copyright (c) 2022 OpenHW Group
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Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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https://solderpad.org/licenses/
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
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This is the CVA6 documentation master file.
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CVA6: An application class RISC-V CPU core
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==========================================
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The goal of the CVA6 project is create a family of production quality, open source, application class RISC-V CPU cores.
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The CVA6 targets both ASIC and FPGA implementations, although individual cores may target a specific implementation technology.
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The CVA6 is written in SystemVerilog and is heavily parameterizable.
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For example parameters can set the ILEN to be either 32- or 64-bits and support for floating point can be enabled/disabled.
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CORE-V Nomenclature
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-------------------
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**CORE-V** is the name of the OpenHW Group family of RISC-V cores.
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CVA6 is the name of a GitHub repository for the source code for a set of application class CORE-V cores.
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The CV prefix identifies it as a member of the CORE-V family and the A6 indicates that it is an application class processor with a six stage execution pipeline.
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However, the CVA6 "as is" is not intended to implement a specific production core.
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Rather, the CVA6 is expected to be the basis for a number of application class cores.
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The naming convention for these cores is:
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``CV <ILEN> <class> <# of pipeline stages> <product identifier>``
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Thus, the CV64A60 would be a 64-bit application core with a six stage pipeline.
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Note that in this example, the product identifer is "0".
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Organization of this Document
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-----------------------------
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This documentation is split into multiple parts.
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The :doc:`CVA6 User Guide <01_cva6_user/index>` provides a detailed introduction to the CVA6.
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This document is based on the original Ariane documentation and is aimed at hardware developers integrating CVA6 into a design.
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The :doc:`CVA6 Requirements Specification <02_cva6_requirements/cva6_requirements_specification>` is the top-level specification of the CVA6.
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One of the key attributes of this document is to specify the feature set of specific CORE-V products based on CVA6.
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This document focuses on _what_ the CVA6 does, without detailed consideration of _how_ a specific requirement is implemented.
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The target audience of this document is current and existing members of the OpenHW Group who wish to participate in the definition of future cores based on the CVA6.
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The :doc:`CVA6 Design Document <03_cva6_design/index>` describes in detail the **CVA6**, the code base that can be used to compile/synthesize a specific core instance (e.g. cv32a65x).
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The :doc:`CV32A65X Design Document <04_cv32a65x/design/source/index>` describes in detail the **CV32A65X**, a specific core based on the CVA6 and the first production quality 32-bit application processor derived from the CVA6.
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The primary audience for this documentation are design and verification engineers working to bring the CV32A65X to TRL-5.
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The :doc:`CVA6 APU <05_cva6_apu/index>` describes an Application Processor Unit built around the CVA6.
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.. toctree::
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:maxdepth: 2
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:hidden:
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02_cva6_requirements/cva6_requirements_specification.rst
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01_cva6_user/index.rst
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03_cva6_design/index.rst
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04_cv32a65x/index.rst
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05_cva6_apu/index.rst
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