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60 lines
2.3 KiB
Systemverilog
60 lines
2.3 KiB
Systemverilog
// Copyright 2022 Thales DIS design services SAS
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//
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// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
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// You may obtain a copy of the License at https://solderpad.org/licenses/
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//
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// Original Author: Jean-Roch COULON - Thales
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module tc_sram_wrapper #(
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parameter int unsigned NumWords = 32'd1024, // Number of Words in data array
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parameter int unsigned DataWidth = 32'd128, // Data signal width
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parameter int unsigned ByteWidth = 32'd8, // Width of a data byte
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parameter int unsigned NumPorts = 32'd2, // Number of read and write ports
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parameter int unsigned Latency = 32'd1, // Latency when the read data is available
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parameter SimInit = "none", // Simulation initialization
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parameter bit PrintSimCfg = 1'b0, // Print configuration
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// DEPENDENT PARAMETERS, DO NOT OVERWRITE!
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parameter int unsigned AddrWidth = (NumWords > 32'd1) ? $clog2(NumWords) : 32'd1,
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parameter int unsigned BeWidth = (DataWidth + ByteWidth - 32'd1) / ByteWidth, // ceil_div
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parameter type addr_t = logic [AddrWidth-1:0],
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parameter type data_t = logic [DataWidth-1:0],
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parameter type be_t = logic [BeWidth-1:0]
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) (
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input logic clk_i, // Clock
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input logic rst_ni, // Asynchronous reset active low
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// input ports
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input logic [NumPorts-1:0] req_i, // request
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input logic [NumPorts-1:0] we_i, // write enable
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input addr_t [NumPorts-1:0] addr_i, // request address
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input data_t [NumPorts-1:0] wdata_i, // write data
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input be_t [NumPorts-1:0] be_i, // write byte enable
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// output ports
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output data_t [NumPorts-1:0] rdata_o // read data
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);
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// synthesis translate_off
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tc_sram #(
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.NumWords(NumWords),
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.DataWidth(DataWidth),
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.ByteWidth(ByteWidth),
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.NumPorts(NumPorts),
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.Latency(Latency),
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.SimInit(SimInit),
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.PrintSimCfg(PrintSimCfg)
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) i_tc_sram (
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.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
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.req_i ( req_i ),
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.we_i ( we_i ),
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.be_i ( be_i ),
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.wdata_i ( wdata_i ),
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.addr_i ( addr_i ),
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.rdata_o ( rdata_o )
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);
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// synthesis translate_on
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endmodule
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