mirror of
https://github.com/openhwgroup/cva6.git
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7cd183b710
using verible-v0.0-3422-g520ca4b9/bin/verible-verilog-format with default configuration Note: two files are not correctly handled by verible - core/include/std_cache_pkg.sv - core/cache_subsystem/cva6_hpdcache_if_adapter.sv
83 lines
3.1 KiB
Systemverilog
83 lines
3.1 KiB
Systemverilog
// Copyright 2018 ETH Zurich and University of Bologna.
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// Copyright and related rights are licensed under the Solderpad Hardware
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// License, Version 0.51 (the "License"); you may not use this file except in
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// compliance with the License. You may obtain a copy of the License at
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// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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// or agreed to in writing, software, hardware and materials distributed under
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// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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// CONDITIONS OF ANY KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations under the License.
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//
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// Engineer: Francesco Conti - f.conti@unibo.it
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//
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// Additional contributions by:
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// Markus Wegmann - markus.wegmann@technokrat.ch
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//
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// Design Name: RISC-V register file
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// Project Name: zero-riscy
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// Language: SystemVerilog
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//
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// Description: Register file with 31 or 15x 32 bit wide registers.
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// Register 0 is fixed to 0. This register file is based on
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// flip flops.
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//
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module ariane_regfile #(
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parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
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parameter int unsigned DATA_WIDTH = 32,
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parameter int unsigned NR_READ_PORTS = 2,
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parameter bit ZERO_REG_ZERO = 0
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) (
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// clock and reset
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input logic clk_i,
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input logic rst_ni,
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// disable clock gates for testing
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input logic test_en_i,
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// read port
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input logic [ NR_READ_PORTS-1:0][ 4:0] raddr_i,
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output logic [ NR_READ_PORTS-1:0][DATA_WIDTH-1:0] rdata_o,
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// write port
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input logic [CVA6Cfg.NrCommitPorts-1:0][ 4:0] waddr_i,
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input logic [CVA6Cfg.NrCommitPorts-1:0][DATA_WIDTH-1:0] wdata_i,
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input logic [CVA6Cfg.NrCommitPorts-1:0] we_i
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);
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localparam ADDR_WIDTH = 5;
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localparam NUM_WORDS = 2 ** ADDR_WIDTH;
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logic [ NUM_WORDS-1:0][DATA_WIDTH-1:0] mem;
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logic [CVA6Cfg.NrCommitPorts-1:0][ NUM_WORDS-1:0] we_dec;
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always_comb begin : we_decoder
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for (int unsigned j = 0; j < CVA6Cfg.NrCommitPorts; j++) begin
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for (int unsigned i = 0; i < NUM_WORDS; i++) begin
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if (waddr_i[j] == i) we_dec[j][i] = we_i[j];
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else we_dec[j][i] = 1'b0;
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end
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end
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end
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// loop from 1 to NUM_WORDS-1 as R0 is nil
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always_ff @(posedge clk_i, negedge rst_ni) begin : register_write_behavioral
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if (~rst_ni) begin
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mem <= '{default: '0};
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end else begin
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for (int unsigned j = 0; j < CVA6Cfg.NrCommitPorts; j++) begin
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for (int unsigned i = 0; i < NUM_WORDS; i++) begin
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if (we_dec[j][i]) begin
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mem[i] <= wdata_i[j];
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end
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end
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if (ZERO_REG_ZERO) begin
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mem[0] <= '0;
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end
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end
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end
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end
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for (genvar i = 0; i < NR_READ_PORTS; i++) begin
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assign rdata_o[i] = mem[raddr_i[i]];
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end
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endmodule
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