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https://github.com/openhwgroup/cva6.git
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b258d27816
Following what was done in branch_unit, I set up a default value for hypervisor exception fields in cvxif_fu. Should fix issue #2831 --------- Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com> Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
79 lines
3.2 KiB
Systemverilog
79 lines
3.2 KiB
Systemverilog
// Copyright 2024 Thales DIS France SAS
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//
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// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
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// You may obtain a copy of the License at https://solderpad.org/licenses/
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//
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// Original Author: Guillaume Chauvon
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// Functional Unit for the CoreV-X-Interface
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// Handles Result interface and exception forwarding to next stages.
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module cvxif_fu
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import ariane_pkg::*;
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#(
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parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
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parameter type exception_t = logic,
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parameter type x_result_t = logic
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) (
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// Subsystem Clock - SUBSYSTEM
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input logic clk_i,
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// Asynchronous reset active low - SUBSYSTEM
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input logic rst_ni,
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// Virtualization mode state - CSR_REGFILE
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input logic v_i,
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// CVXIF instruction is valid - ISSUE_STAGE
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input logic x_valid_i,
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// Transaction ID - ISSUE_STAGE
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input logic [CVA6Cfg.TRANS_ID_BITS-1:0] x_trans_id_i,
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// Instruction is illegal, determined during CVXIF issue transaction - ISSUE_STAGE
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input logic x_illegal_i,
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// Offloaded instruction - ISSUE_STAGE
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input logic [ 31:0] x_off_instr_i,
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// CVXIF is ready - ISSUE_STAGE
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output logic x_ready_o,
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// CVXIF result transaction ID - ISSUE_STAGE
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output logic [CVA6Cfg.TRANS_ID_BITS-1:0] x_trans_id_o,
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// CVXIF exception - ISSUE_STAGE
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output exception_t x_exception_o,
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// CVXIF FU result - ISSUE_STAGE
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output logic [ CVA6Cfg.XLEN-1:0] x_result_o,
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// CVXIF result valid - ISSUE_STAGE
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output logic x_valid_o,
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// CVXIF write enable - ISSUE_STAGE
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output logic x_we_o,
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// CVXIF destination register - ISSUE_STAGE
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output logic [ 4:0] x_rd_o,
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// CVXIF result interface
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input logic result_valid_i,
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input x_result_t result_i,
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output logic result_ready_o
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);
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assign result_ready_o = 1'b1;
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assign x_ready_o = 1'b1; // Readyness of cvxif_fu is determined in issue stage by CVXIF issue interface
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// Result signals
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assign x_valid_o = x_illegal_i || result_valid_i;
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assign x_result_o = result_i.data;
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assign x_trans_id_o = x_illegal_i ? x_trans_id_i : result_i.id;
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assign x_we_o = result_i.we;
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assign x_rd_o = result_i.rd;
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// Handling of illegal instruction exception
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always_comb begin
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x_exception_o.valid = x_illegal_i;
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x_exception_o.cause = x_illegal_i ? riscv::ILLEGAL_INSTR : '0;
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if (CVA6Cfg.TvalEn)
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x_exception_o.tval = x_off_instr_i; // TODO Optimization : Set exception in IRO.
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// Hypervisor exception fields
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x_exception_o.tval2 = {CVA6Cfg.GPLEN{1'b0}};
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x_exception_o.tinst = '0;
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x_exception_o.gva = CVA6Cfg.RVH ? v_i : 1'b0;
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end
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endmodule
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