cva6/core/frontend
Riccardo Tedeschi ed24d814eb
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bht2lvl: refactor code to work with Verilator (#3028)
bht2lvl containts a coding pattern that is not supported in Verilator, despite being legal
Unsupported: Delayed assignment to array inside for loops (non-delayed is ok - see docs)
This issue is not always triggered, as it popped up for cv64 but not for cv32.
2025-06-25 00:19:03 +02:00
..
bht.sv Altera opt 2 (#2602) 2024-11-21 23:36:18 +01:00
bht2lvl.sv bht2lvl: refactor code to work with Verilator (#3028) 2025-06-25 00:19:03 +02:00
btb.sv Fixed btb for FPGA targets (#2521) 2024-10-02 23:31:40 +02:00
frontend.sv [Fix] fence.i fails to synchronize ICache/DCache flushes in write-back mode (#2971) 2025-05-21 13:30:28 +02:00
instr_queue.sv remove ifndef VERILATOR (#2686) 2025-01-08 09:08:44 +01:00
instr_scan.sv doc: fix description of signals in instr_scan.sv (#2752) 2025-01-31 05:44:24 +01:00
ras.sv Parametrization step 3 part 2 (#1939) 2024-03-18 12:06:55 +01:00