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308 lines
9.6 KiB
Text
308 lines
9.6 KiB
Text
[[cva6_cvx_interface_coprocessor]]
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CV-X-IF Interface and Coprocessor
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The CV-X-IF interface of CVA6 allows to extend its supported instruction
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set with external coprocessors.
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_Applicability of this chapter to configurations:_
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[cols=",",options="header",]
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|=============================
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|Configuration |Implementation
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|CV32A60AX |CV-X-IF included
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|CV32A60X |CV-X-IF included
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|CV64A6_MMU |CV-X-IF included
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|=============================
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[[cv-x-if-interface-specification]]
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CV-X-IF interface specification
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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[[description]]
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Description
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+++++++++++
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This design specification presents global functionalities of
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Core-V-eXtension-Interface (XIF, CVXIF, CV-X-IF, X-interface) in the CVA6 core.
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[source,sourceCode,text]
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----
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The CORE-V X-Interface is a RISC-V eXtension interface that provides a
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generalized framework suitable to implement custom coprocessors and ISA
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extensions for existing RISC-V processors.
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--core-v-xif Readme, https://github.com/openhwgroup/core-v-xif
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----
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The specification of the CV-X-IF bus protocol can be found at [CV-X-IF].
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CV-X-IF aims to:
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* Create interfaces to connect a coprocessor to the CVA6 to execute instructions.
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* Offload CVA6 illegal instrutions to the coprocessor to be executed.
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* Get the results of offloaded instructions from the coprocessor so they are written back into the CVA6 register file.
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* Add standard RISC-V instructions unsupported by CVA6 or custom instructions and implement them in a coprocessor.
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* Kill offloaded instructions to allow speculative execution in the coprocessor. (Unsupported in CVA6 yet)
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* Connect the coprocessor to memory via the CVA6 Load and Store Unit. (Unsupported in CVA6 yet)
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The coprocessor operates like another functional unit so it is connected
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to the CVA6 in the execute stage.
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Only the 3 mandatory interfaces from the CV-X-IF specification (issue, commit and result
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) have been implemented.
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Compressed interface, Memory Interface and Memory result interface are not yet
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implemented in the CVA6.
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[[supported-parameters]]
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Supported Parameters
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++++++++++++++++++++
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The following table presents CVXIF parameters supported by CVA6.
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[cols=",a,a",options="header",]
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|=============================================
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|Signal |Value |Description
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|*X_NUM_RS* |
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int: 2 or 3 (configurable) +
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* CV32A60X: 2
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* CV32A65X: 2
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[verse]
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--
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Number of register file read ports that can
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be used by the eXtension interface
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--
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|*X_ID_WIDTH* |
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int: 1 to 32 +
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* CV32A60X: 2
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* CV32A65X: 3
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[verse]
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--
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Identification width for the eXtension
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interface
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--
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|*X_MEM_WIDTH* |n/a (feature not supported) |
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[verse]
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--
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Memory access width for loads/stores via the
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eXtension interface
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--
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|*X_RFR_WIDTH* |
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int: `XLEN` (32 or 64) +
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* CV32A60X: 32
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* CV32A65X: 32
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[verse]
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--
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Register file read access width for the
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eXtension interface
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--
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|*X_RFW_WIDTH* |
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int: `XLEN` (32 or 64) +
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* CV32A60X: 32
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* CV32A65X: 32
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[verse]
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--
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Register file write access width for the
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eXtension interface
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--
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|*X_MISA* |logic[31:0]: 0x0000_0000 |
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[verse]
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--
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MISA extensions implemented on the eXtension
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interface
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--
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|=============================================
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[[cv-x-if-enabling]]
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CV-X-IF Enabling
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++++++++++++++++
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CV-X-IF can be enabled or disabled via the `CVA6ConfigCvxifEn` parameter in the SystemVerilog source code.
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[[illegal-instruction-decoding]]
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Illegal instruction decoding
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++++++++++++++++++++++++++++
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The CVA6 decoder module detects illegal instructions for the CVA6, prepares exception field
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with relevant information (exception code "ILLEGAL INSTRUCTION", instruction value).
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The exception valid flag is raised in CVA6 decoder when CV-X-IF is disabled. Otherwise
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it is not raised at this stage because the decision belongs to the coprocessor
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after the offload process.
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[[rs3-support]]
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RS3 support
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+++++++++++
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The number of source registers used by the CV-X-IF coprocessor is configurable with 2 or
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3 source registers.
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If CV-X-IF is enabled and configured with 3 source registers,
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a third read port is added to the CVA6 general purpose register file.
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[[description-of-interface-connections-between-cva6-and-coprocessor]]
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Description of interface connections between CVA6 and Coprocessor
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+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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In CVA6 execute stage, there is a new functional unit dedicated to drive the CV-X-IF interfaces.
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Here is _how_ and _to what_ CV-X-IF interfaces are connected to the CVA6.
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* Issue interface::
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** Request;;
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*** [verse]
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--
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Operands are connected to `issue_req.rs` signals
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--
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*** [verse]
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--
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Scoreboard transaction id is connected to `issue_req.id` signal.
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Therefore scoreboard ids and offloaded instruction ids are linked
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together (equal in this implementation). It allows the CVA6 to do out
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of order execution with the coprocessor in the same way as other
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functional units.
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--
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*** [verse]
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--
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Undecoded instruction is connected to `issue_req.instruction`
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--
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*** [verse]
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--
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Valid signal for CVXIF functional unit is connected to
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`issue_req.valid`
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--
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*** [verse]
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--
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All `issue_req.rs_valid` signals are set to 1. The validity of source
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registers is assured by the validity of valid signal sent from issue stage.
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--
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** Response;;
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*** [verse]
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--
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If `issue_resp.accept` is set during a transaction (i.e. issue valid
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and ready are set), the offloaded instruction is accepted by the coprocessor
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and a result transaction will happen.
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--
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*** [verse]
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--
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If `issue_resp.accept` is not set during a transaction, the offloaded
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instruction is illegal and an illegal instruction exception will be
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raised as soon as no result transaction are written on the writeback bus.
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--
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* Commit interface::
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** [verse]
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--
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Valid signal of commit interface is connected to the valid signal of
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issue interface.
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--
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** [verse]
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--
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Id signal of commit interface is connected to issue interface id signal
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(i.e. scoreboard id).
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--
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** [verse]
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--
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Killing of offload instruction is never set. (Unsupported feature)
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--
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** [verse]
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--
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Therefore all accepted offloaded instructions are commited to their
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execution and no killing of instruction is possible in this implementation.
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--
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* Result interface::
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** Request;;
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*** [verse]
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--
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Ready signal of result interface is always set as CVA6 is always ready
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to take a result from coprocessor for an accepted offloaded instruction.
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--
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** Response;;
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*** [verse]
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--
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Result response is directly connected to writeback bus of the CV-X-IF
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functionnal unit.
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--
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*** [verse]
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--
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Valid signal of result interface is connected to valid signal of
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writeback bus.
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--
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*** [verse]
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--
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Id signal of result interface is connected to scoreboard id of
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writeback bus.
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--
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*** [verse]
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--
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Write enable signal of result interface is connected to a dedicated CV-X-IF WE
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signal in CVA6 which signals scoreboard if a writeback should happen
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or not to the CVA6 register file.
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--
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*** [verse]
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--
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`exccode` and `exc` signal of result interface are connected to exception
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signals of writeback bus. Exception from coprocessor does not write
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the `tval` field in exception signal of writeback bus.
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--
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*** [verse]
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--
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Three registers are added to hold illegal instruction information in
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case a result transaction and a non-accepted issue transaction happen
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in the same cycle. Result transactions will be written to the writeback
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bus in this case having priority over the non-accepted instruction due
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to being linked to an older offloaded instruction. Once the writeback
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bus is free, an illegal instruction exception will be raised thanks to
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information held in these three registers.
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--
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[[coprocessor-recommendations-for-use-with-cva6s-cv-x-if]]
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Coprocessor recommendations for use with CVA6's CV-X-IF
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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CVA6 supports all coprocessors supporting the CV-X-IF specification with the exception of :
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* Coprocessor requiring the Memory interface and Memory result interface (not implemented in CVA6 yet).::
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** All memory transaction should happen via the Issue interface, i.e. Load into CVA6 register file
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then initialize an issue transaction.
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* Coprocessor requiring the Compressed interface (not implemented in CVA6 yet).::
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** RISC-V Compressed extension (RVC) is already implemented in CVA6 User Space for custom compressed instruction
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is not big enough to have RVC and a custom compressed extension.
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* Stateful coprocessors.::
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** CVA6 will commit on the Commit interface all its issue transactions. Speculation
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informations are only kept in the CVA6 and speculation process is only done in CVA6.
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The coprocessor shall be stateless otherwise it will not be able to revert its state if CVA6 kills an
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in-flight instruction (in case of mispredict or flush).
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[[how-to-use-cva6-without-cv-x-if-interface]]
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How to use CVA6 without CV-X-IF interface
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Select a configuration with `CVA6ConfigCvxifEn` parameter disabled or change it for your configuration.
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Never let the CV-X-IF interface unconnected with the `CVA6ConfigCvxifEn` parameter enabled.
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[[how-to-design-a-coprocessor-for-the-cv-x-if-interface]]
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How to design a coprocessor for the CV-X-IF interface
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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_The team is looking for a contributor to write this section._
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[[how-to-program-a-cv-x-if-coprocessor]]
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How to program a CV-X-IF coprocessor
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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_The team is looking for a contributor to write this section._
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