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129 lines
4 KiB
Text
129 lines
4 KiB
Text
[[traps-interrupts-exceptions]]
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Traps, Interrupts, Exceptions
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Traps are composed of interrupts and exceptions.
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Interrupts are asynchronous events whereas exceptions are synchronous ones.
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On one hand, interrupts are occuring independently of the instructions
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(mainly raised by peripherals or debug module).
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On the other hand, an instruction may raise exceptions synchronously.
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[[raising-traps]]
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Raising Traps
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^^^^^^^^^^^^^
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When a trap is raised, the behaviour of the CVA6 core depends on
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several CSRs and some CSRs are modified.
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[[configuration-csrs]]
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Configuration CSRs
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++++++++++++++++++
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CSRs having an effect on the core behaviour when a trap occurs are:
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* `mstatus` and `sstatus`: several fields control the core behaviour like interrupt enable (`MIE`, `SIE`)
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* `mtvec` and `stvec`: specifies the address of trap handler.
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* `medeleg`: specifies which exceptions can be handled by a lower privileged mode (S-mode)
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* `mideleg`: specifies which interrupts can be handled by a lower privileged mode (S-mode)
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[[modified-csrs]]
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Modified CSRs
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+++++++++++++
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CSRs (or fields) updated by the core when a trap occurs are:
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* `mstatus` or `sstatus`: several fields are updated like previous privilege mode (`MPP`, `SPP`), previous interrupt enabled (`MPIE`, SPIE``)
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* `mepc` or `sepc`: updated with the virtual address of the interrupted instruction or the instruction raising the exception.
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* `mcause` or `scause`: updated with a code indicating the event causing the trap.
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* `mtval` or `stval`: updated with exception specific information like the faulting virtual address
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[[supported-exceptions]]
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Supported exceptions
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++++++++++++++++++++
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The following exceptions are supported by the CVA6:
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* instruction address misaligned
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** control flow instruction with misaligned target
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* instruction access fault
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** access to PMP region without execute permissions
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* illegal instruction:
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** unimplemented CSRs
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** unsupported extensions
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* breakpoint (`EBREAK`)
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* load address misaligned:
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** `LH` at 2n+1 address
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** `LW` at 4n+1, 4n+2, 4n+3 address
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* load access fault
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** access to PMP region without read permissions
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* store/AMO address misaligned
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** `SH` at 2n+1 address
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** `SW` at 4n+1, 4n+2, 4n+3 address
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* store/AMO access fault
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** access to PMP region without write permissions
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* environment call (`ECALL`) from U-mode
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* environment call (`ECALL`) from S-mode
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* environment call (`ECALL`) from M-mode
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* instruction page fault
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* load page fault
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** access to effective address without read permissions
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* store/AMO page fault
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** access to effective address without write permissions
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* debug request (custom) via debug interface
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Note: all exceptions are supported except the ones linked to the hypervisor extension
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[[trap-return]]
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Trap return
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^^^^^^^^^^^
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Trap handler ends with trap return instruction (`MRET`, `SRET`). The behaviour of the CVA6 core depends on several CSRs.
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[[configuration-csrs-1]]
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Configuration CSRs
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++++++++++++++++++
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CSRs having an effect on the core behaviour when returning from a trap are:
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* `mstatus`: several fields control the core behaviour like previous privilege mode (`MPP`, `SPP`), previous interrupt enabled (`MPIE`, `SPIE`)
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[[modified-csrs-1]]
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Modified CSRs
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+++++++++++++
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CSRs (or fields) updated by the core when returning from a trap are:
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* `mstatus`: several fields are updated like interrupt enable (`MIE`, `SIE`), modify privilege (`MPRV`)
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[[interrupts]]
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Interrupts
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^^^^^^^^^^
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* external interrupt: `irq_i` signal
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* software interrupt (inter-processor interrupt): `ipi_i` signal
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* timer interrupt: `time_irq_i` signal
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* debug interrupt: `debug_req_i` signal
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These signals are level sensitive. It means the interrupt is raised until it is cleared.
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The exception code field (`mcause` CSR) depends on the interrupt source.
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[[wait-for-interrupt]]
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Wait for Interrupt
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^^^^^^^^^^^^^^^^^^
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* CVA6 implementation: `WFI` stalls the core. The instruction is not available in U-mode (raise illegal instruction exception). Such exception is also raised when `TW=1` in `mstatus`.
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