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64 lines
2.3 KiB
Text
64 lines
2.3 KiB
Text
[[glossary]]
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Glossary
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--------
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* *ALU*: Arithmetic/Logic Unit
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* *APU*: Application Processing Unit
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* *ASIC*: Application-Specific Integrated Circuit
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* *AXI*: Advanced eXtensible Interface
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* *BHT*: Branch History Table
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* *BTB*: Branch Target Buffer
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* *Byte*: 8-bit data item
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* *CPU*: Central Processing Unit, processor
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* *CSR*: Control and Status Register
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* *Custom extension*: Non-Standard extension to the RISC-V base
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instruction set (RISC-V Instruction Set Manual, Volume I: User-Level
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ISA)
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* *CVA6*: Core-V Application class processor with a 6 stage pipeline
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* *D$*: Data Cache
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* *DPI*: Direct Programming Interface
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* *EX* or *EXE*: Instruction Execute
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* *FPGA*: Field Programmable Gate Array
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* *FPU*: Floating Point Unit
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* *Halfword*: 16-bit data item
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* *Halfword aligned address*: An address is halfword aligned if it is
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divisible by 2
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* *I$*: Instruction Cache
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* *ID*: Instruction Decode
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* *IF*: Instruction Fetch
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* *ISA*: Instruction Set Architecture
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* *KGE*: Kilo Gate Equivalents (NAND2)
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* *LSU*: Load Store Unit
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* *M-Mode*: Machine Mode (RISC-V Instruction Set Manual, Volume II:
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Privileged Architecture)
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* *MMU*: Memory Management Unit
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* *NC*: Not Cacheable
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* *OBI*: Open Bus Interface
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* *OoO*: Out Of Order
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* *PC*: Program Counter
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* *PMP*: Physical memory protection (RISC-V Instruction Set Manual,
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Volume II: Privileged Architecture)
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* *PTW*: Page Table Walker
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* *PULP platform*: Parallel Ultra Low Power Platform
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(<https://pulp-platform.org>)
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* *RAS*: Return Address Stack
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* *RV32C*: RISC-V Compressed (C extension)
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* *RV32F*: RISC-V Floating Point (F extension)
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* *S-Mode*: Supervisor Mode (RISC-V Instruction Set Manual, Volume II:
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Privileged Architecture)
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* *SIMD*: Single Instruction/Multiple Data
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* *Standard extension*: Standard extension to the RISC-V base
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instruction set (RISC-V Instruction Set Manual, Volume I: User-Level
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ISA)
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* *TLB*: Translation Lookaside Buffer
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* *U-Mode*: User Mode (RISC-V Instruction Set Manual, Volume II:
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Privileged Architecture)
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* *VLEN*: Virtual address length
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* *WARL*: Write Any Values, Reads Legal Values
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* *WB*: Write Back of instruction results
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* *WLRL*: Write/Read Only Legal Values
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* *Word*: 32-bit data item
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* *Word aligned address*: An address is word aligned if it is divisible
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by 4
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* *WPRI*: Reserved Writes Preserve Values, Reads Ignore Values
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* *XLEN*: RISC-V processor data length
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