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51 lines
1.5 KiB
Text
51 lines
1.5 KiB
Text
////
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Copyright 2022 Thales DIS design services SAS
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Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
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You may obtain a copy of the License at https://solderpad.org/licenses/
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Original Author: Jean-Roch COULON - Thales
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////
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[[subsystem]]
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Subsystem
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---------
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[[global-functionality]]
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Global functionality
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~~~~~~~~~~~~~~~~~~~~
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The CVA6 is a subsystem composed of the modules and protocol interfaces
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as illustrated The processor is a Harvard-based modern architecture.
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Instructions are issued in-order through the DECODE stage and executed
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out-of-order but committed in-order. The processor is Single issue, that
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means that at maximum one instruction per cycle can be issued to the
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EXECUTE stage.
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The CVA6 implements a 6-stage pipeline composed of PC Generation,
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Instruction Fetch, Instruction Decode, Issue stage, Execute stage and
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Commit stage. At least 6 cycles are needed to execute one instruction.
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[[connection-with-other-sub-systems]]
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Connection with other sub-systems
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The submodule is connected to :
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* NOC interconnect provides memory content
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* COPROCESSOR connects through CV-X-IF coprocessor interface protocol
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* TRACER provides support for verification
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* TRAP provides traps inputs
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[[parameter-configuration]]
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Parameter configuration
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~~~~~~~~~~~~~~~~~~~~~~~
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include::parameters.adoc[]
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[[io-ports]]
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IO ports
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~~~~~~~~
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include::port_cva6.adoc[]
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