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102 lines
4 KiB
Tcl
102 lines
4 KiB
Tcl
# Copyright 2021 Thales DIS design services SAS
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#
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# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
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# You may obtain a copy of the License at https://solderpad.org/licenses/
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#
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# Original Author: Jean-Roch COULON - Thales
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#
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# Variables common to all reference methodology scripts
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set PERIOD [getenv PERIOD];
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set DESIGN_NAME [getenv DESIGN_NAME] ;# The name of the top-level design
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set TARGET [getenv TARGET];
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set TECH [getenv TECH_NAME];
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set techno [getenv TECH_NAME];
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set FOUNDRY_PATH [getenv FOUNDRY_PATH];
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set TARGET_LIBRARY_FILES [getenv TARGET_LIBRARY_FILES];
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set INPUT_DELAY [getenv INPUT_DELAY];
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set OUTPUT_DELAY [getenv OUTPUT_DELAY];
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set LOCAL_LIB_PATH [getenv LOCAL_LIB_PATH];
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set ADDITIONAL_LINK_LIB_FILES " ";# Extra link logical libraries not included in TARGET_LIBRARY_FILES
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# Remove messages
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suppress_message LINK-17
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suppress_message MWLIBP-300
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suppress_message MWLIBP-301
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suppress_message MWLIBP-319
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suppress_message MWLIBP-319
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suppress_message MWLIBP-324
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suppress_message MWLIBP-311
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suppress_message MWLIBP-032
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suppress_message UCN-1
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suppress_message UID-282
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set ADDITIONAL_SEARCH_PATH " ${FOUNDRY_PATH}/synopsys ${FOUNDRY_PATH} ";
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set_app_var search_path ". ${ADDITIONAL_SEARCH_PATH} $search_path"
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if {$synopsys_program_name == "dc_shell"} {
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set_app_var target_library ${TARGET_LIBRARY_FILES}
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set_app_var synthetic_library dw_foundation.sldb
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set_app_var link_library "* $target_library $ADDITIONAL_LINK_LIB_FILES $synthetic_library"
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}
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source -echo -verbose scripts/dc_setup_filenames.tcl
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# The following setting removes new variable info messages from the end of the log file
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set_app_var sh_new_variable_message false
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if {$synopsys_program_name == "dc_shell"} {
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#################################################################################
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# Design Compiler Setup Variables
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#################################################################################
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# Use the set_host_options command to enable multicore optimization to improve runtime.
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# This feature has special usage and license requirements. Refer to the
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# "Support for Multicore Technology" section in the Design Compiler User Guide
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# for multicore usage guidelines.
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# Note: This is a DC Ultra feature and is not supported in DC Expert.
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set_host_options -max_cores 8
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# Change alib_library_analysis_path to point to a central cache of analyzed libraries
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# to save runtime and disk space. The following setting only reflects the
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# default value and should be changed to a central location for best results.
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set_app_var alib_library_analysis_path .
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# Add any additional Design Compiler variables needed here
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define_name_rules verilog \
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-target_bus_naming_style "%s\[%d\]" \
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-allowed "a-z0-9_" \
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-first_restricted "0-9_" \
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-replacement_char "_" \
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-equal_ports_nets -inout_ports_equal_nets \
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-collapse_name_space -case_insensitive -special verilog \
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-add_dummy_nets \
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-dummy_net_prefix "synp_unconn_%d"
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# Eliminate tri-state nets and assign primitives in the output netlist"
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set_app_var verilogout_no_tri true
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# Preserve FF with not load used as spare"
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set_app_var hdlin_preserve_sequential ff+loop_variables
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### Power optim
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set_app_var power_remove_redundant_clock_gates true
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set_app_var power_cg_reconfig_stages true
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set_app_var compile_clock_gating_through_hierarchy true
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set_app_var power_cg_designware true
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set_app_var power_cg_derive_related_clock true
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set_app_var do_operand_isolation true
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set_app_var power_low_power_placement true
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set_app_var power_opto_extra_high_dynamic_power_effort true
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### Module name naming style
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set_app_var template_parameter_style "%s"
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set_app_var template_naming_style "%s"
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}
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