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70 lines
3.2 KiB
Makefile
70 lines
3.2 KiB
Makefile
# Copyright 2021 Thales DIS design services SAS
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#
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# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
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# You may obtain a copy of the License at https://solderpad.org/licenses/
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#
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# Original Author: Jean-Roch COULON - Thales
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#
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DESIGN_NAME ?= cva6
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PERIOD ?= 17
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FOUNDRY_PATH ?=
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LOCAL_LIB_PATH ?=/shares/common/tools/RAMs/
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TARGET_LIBRARY_FILES = $(TECH_NAME).db
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INPUT_DELAY ?= 0.46
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OUTPUT_DELAY ?= 0.11
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DC_SHELL_PATH ?= /opt/synopsys/syn/Q-2019.12/bin/
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NAND2_AREA ?= 1120
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TARGET ?= cv32a65x
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EXPORT_LIST=SNPSLMD_QUEUE=TRUE TECH_NAME=$(TECH_NAME) DESIGN_NAME=$(DESIGN_NAME) TARGET=$(TARGET) TERM=vt100 PERIOD=$(PERIOD) FOUNDRY_PATH=$(FOUNDRY_PATH) LOCAL_LIB_PATH=$(LOCAL_LIB_PATH) TARGET_LIBRARY_FILES=$(TARGET_LIBRARY_FILES) INPUT_DELAY=$(INPUT_DELAY) OUTPUT_DELAY=$(OUTPUT_DELAY)
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ifndef FOUNDRY_PATH
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$(error "Please provide FOUNDRY techno")
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endif
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ifndef TECH_NAME
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$(error "Please provide TECH_NAME techno")
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endif
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# Create Flist with good compilation order for synthesis
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# - config_pkg.sv
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# - hpdcache_params_pkg.sv before hdpcache_pkg.sv
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# - pkg before rtl
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pre_cva6_synth:
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grep "{\w*}" ../../core/Flist.cva6|grep -v "instr_tracer"|grep -v "incdir"|grep -v "hpdcache.Flist" > Flist.cva6_synth
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grep "{\w*}" ../../core/cache_subsystem/hpdcache/rtl/hpdcache.Flist|grep -v "incdir" >> Flist.cva6_synth
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grep "hpdcache_pkg.sv" Flist.cva6_synth > hpdcache_pkg.tmp
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grep "_pkg.sv" Flist.cva6_synth | grep -v "hpdcache_pkg.sv" > packages.tmp
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grep -v "hpdcache_pkg.sv" Flist.cva6_synth | grep -v "HPDCACHE_TARGET_CFG" | grep -v "_pkg.sv" > rtl.tmp
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cat packages.tmp > Flist.cva6_synth
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cat hpdcache_pkg.tmp >> Flist.cva6_synth
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cat rtl.tmp >> Flist.cva6_synth
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sed -i "s/^/analyze -f sverilog -lib ariane_lib -define HPDCACHE_ASSERT_OFF /" Flist.cva6_synth
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sed -i -e 's/behav/blackbox/g' Flist.cva6_synth
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# Deprecated
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cva6_synth: pre_cva6_synth
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@echo $(PERIOD)
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@export $(EXPORT_LIST); $(DC_SHELL_PATH)/dc_shell -f ./cva6_synth.tcl -output synthesis_batch.log
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python scripts/gate_analysis.py '$(DESIGN_NAME)_$(TARGET)/$(PERIOD)/reports/$(DESIGN_NAME)_$(TECH_NAME)_synth_area.rpt' $(NAND2_AREA)
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mv $(DESIGN_NAME)_synth.v $(DESIGN_NAME)_$(TARGET)_synth.v
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mv $(DESIGN_NAME)_synth.v.sdf $(DESIGN_NAME)_$(TARGET)_synth.v.sdf
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sed -i 's/cva6_ /cva6 /g' $(DESIGN_NAME)_$(TARGET)_synth.v
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echo $(NAND2_AREA) > $(DESIGN_NAME)_$(TARGET)/nand2area.txt
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# Supported for cv32a65x
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rm_synth: pre_cva6_synth
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@echo $(PERIOD)
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cp Flist.cva6_synth ../../$(SYNTH_FLOW_NAME)/synth/
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CVA6_REPO_DIR=$(CVA6_REPO_DIR) make -C ../../$(SYNTH_FLOW_NAME)/synth/ platform_synth_topo
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sed -i -n -e '/module hpdcache_sram_wbyteenable_1rw_00000007_00000040_00000080/,/endmodule/!p' $(DESIGN_NAME)_$(TARGET)_synth.v
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sed -i -n -e '/module hpdcache_sram_1rw_00000006_0000001a_00000040/,/endmodule/!p' $(DESIGN_NAME)_$(TARGET)_synth.v
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echo $(NAND2_AREA) > $(DESIGN_NAME)_$(TARGET)/nand2area.txt
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cva6_read:
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@export $(EXPORT_LIST); $(DC_SHELL_PATH)/dc_shell -f cva6_read.tcl -gui
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clean:
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@rm -rf work alib* *_LIB *log *svf netlist reports ${DESIGN_NAME}_${TARGET}
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