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74 lines
2.5 KiB
Text
74 lines
2.5 KiB
Text
////
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Copyright 2024 Thales DIS France SAS
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Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
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you may not use this file except in compliance with the License.
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SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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You may obtain a copy of the License at https://solderpad.org/licenses/
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Original Author: Jean-Roch COULON - Thales
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////
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[[_CVA6_controller_ports]]
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.*controller module* IO ports
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|===
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|Signal | IO | Description | connexion | Type
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|`clk_i` | in | Subsystem Clock | SUBSYSTEM | logic
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|`rst_ni` | in | Asynchronous reset active low | SUBSYSTEM | logic
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|`set_pc_commit_o` | out | Set PC om PC Gen | FRONTEND | logic
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|`flush_if_o` | out | Flush the IF stage | FRONTEND | logic
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|`flush_unissued_instr_o` | out | Flush un-issued instructions of the scoreboard | FRONTEND | logic
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|`flush_id_o` | out | Flush ID stage | ID_STAGE | logic
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|`flush_ex_o` | out | Flush EX stage | EX_STAGE | logic
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|`flush_bp_o` | out | Flush branch predictors | FRONTEND | logic
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|`flush_icache_o` | out | Flush ICache | CACHE | logic
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|`flush_dcache_o` | out | Flush DCache | CACHE | logic
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|`flush_dcache_ack_i` | in | Acknowledge the whole DCache Flush | CACHE | logic
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|`halt_csr_i` | in | Halt request from CSR (WFI instruction) | CSR_REGFILE | logic
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|`halt_o` | out | Halt signal to commit stage | COMMIT_STAGE | logic
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|`eret_i` | in | Return from exception | CSR_REGFILE | logic
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|`ex_valid_i` | in | We got an exception, flush the pipeline | FRONTEND | logic
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|`resolved_branch_i` | in | We got a resolved branch, check if we need to flush the front-end | EX_STAGE | bp_resolve_t
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|`flush_csr_i` | in | We got an instruction which altered the CSR, flush the pipeline | CSR_REGFILE | logic
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|`flush_commit_i` | in | Flush request from commit stage | COMMIT_STAGE | logic
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|===
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Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
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As RVH = False,::
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* `v_i` input is tied to 0
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* `flush_tlb_vvma_o` output is tied to 0
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* `flush_tlb_gvma_o` output is tied to 0
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* `hfence_vvma_i` input is tied to 0
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* `hfence_gvma_i` input is tied to 0
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As MMUPresent = 0,::
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* `flush_tlb_o` output is tied to 0
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As EnableAccelerator = 0,::
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* `halt_acc_i` input is tied to 0
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* `flush_acc_i` input is tied to 0
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As DebugEn = False,::
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* `set_debug_pc_i` input is tied to 0
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As FenceEn = 0,::
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* `fence_i_i` input is tied to 0
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* `fence_i` input is tied to 0
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As RVS = False,::
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* `sfence_vma_i` input is tied to 0
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