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68 lines
2.3 KiB
Text
68 lines
2.3 KiB
Text
////
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Copyright 2024 Thales DIS France SAS
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Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
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you may not use this file except in compliance with the License.
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SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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You may obtain a copy of the License at https://solderpad.org/licenses/
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Original Author: Jean-Roch COULON - Thales
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////
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[[_CVA6_decoder_ports]]
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.*decoder module* IO ports
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|===
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|Signal | IO | Description | connexion | Type
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|`pc_i` | in | PC from fetch stage | FRONTEND | logic[CVA6Cfg.VLEN-1:0]
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|`is_compressed_i` | in | Is a compressed instruction | compressed_decoder | logic
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|`compressed_instr_i` | in | Compressed form of instruction | FRONTEND | logic[15:0]
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|`is_illegal_i` | in | Illegal compressed instruction | compressed_decoder | logic
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|`instruction_i` | in | Instruction from fetch stage | FRONTEND | logic[31:0]
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|`is_macro_instr_i` | in | Is a macro instruction | macro_decoder | logic
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|`is_last_macro_instr_i` | in | Is a last macro instruction | macro_decoder | logic
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|`is_double_rd_macro_instr_i` | in | Is mvsa01/mva01s macro instruction | macro_decoder | logic
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|`branch_predict_i` | in | Is a branch predict instruction | FRONTEND | branchpredict_sbe_t
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|`ex_i` | in | If an exception occured in fetch stage | FRONTEND | exception_t
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|`irq_i` | in | Level sensitive (async) interrupts | SUBSYSTEM | logic[1:0]
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|`irq_ctrl_i` | in | Interrupt control status | CSR_REGFILE | irq_ctrl_t
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|`instruction_o` | out | Instruction to be added to scoreboard entry | ISSUE_STAGE | scoreboard_entry_t
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|`orig_instr_o` | out | Instruction | ISSUE_STAGE | logic[31:0]
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|`is_control_flow_instr_o` | out | Is a control flow instruction | ISSUE_STAGE | logic
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|===
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Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
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As DebugEn = False,::
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* `debug_req_i` input is tied to 0
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* `debug_mode_i` input is tied to 0
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As PRIV = MachineOnly,::
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* `priv_lvl_i` input is tied to MachineMode
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* `tvm_i` input is tied to 0
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* `tw_i` input is tied to 0
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* `tsr_i` input is tied to 0
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As RVH = False,::
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* `v_i` input is tied to 0
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* `vfs_i` input is tied to 0
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* `vtw_i` input is tied to 0
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* `hu_i` input is tied to 0
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As RVF = 0,::
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* `fs_i` input is tied to 0
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* `frm_i` input is tied to 0
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As RVV = False,::
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* `vs_i` input is tied to 0
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