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1793be633e
* ariane: Add conditional rocket chip traceport to top-level * ariane: Add license information
24 lines
577 B
Systemverilog
24 lines
577 B
Systemverilog
// See LICENSE.Berkeley for license details.
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// Author: Abraham Gonzalez, UC Berkeley
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// Date: 24.02.2020
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// Description: Traced Instruction and Port (using in Rocket Chip based systems)
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package traced_instr_pkg;
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typedef struct packed {
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logic clock;
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logic reset;
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logic valid;
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logic [63:0] iaddr;
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logic [31:0] insn;
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logic [1:0] priv;
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logic exception;
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logic interrupt;
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logic [63:0] cause;
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logic [63:0] tval;
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} traced_instr_t;
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typedef traced_instr_t [ariane_pkg::NR_COMMIT_PORTS-1:0] trace_port_t;
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endpackage
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