mirror of
https://github.com/openhwgroup/cva6.git
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248 lines
9.1 KiB
Python
248 lines
9.1 KiB
Python
"""
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Copyright 2019 Google LLC
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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Convert spike sim log to standard riscv instruction trace format
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"""
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import argparse
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import os
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import re
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import sys
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import logging
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sys.path.insert(0, os.path.dirname(os.path.realpath(__file__)))
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from riscv_trace_csv import *
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from lib import *
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RD_RE = re.compile(r"(core\s+\d+:\s+)?(?P<pri>\d) 0x(?P<addr>[a-f0-9]+?) " \
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"\((?P<bin>.*?)\)(( c\S* 0x[a-f0-9]+)*) (?P<reg>[xf]\s*\d*?)\s*0x(?P<val>[a-f0-9]+)")
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CORE_RE = re.compile(
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r"core\s+\d+:\s+0x(?P<addr>[a-f0-9]+?) \(0x(?P<bin>.*?)\) (?P<instr>.*?)$")
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ADDR_RE = re.compile(
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r"(?P<rd>[a-z0-9]+?),(?P<imm>[\-0-9]+?)\((?P<rs1>[a-z0-9]+)\)")
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ILLE_RE = re.compile(r"trap_illegal_instruction")
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LOGGER = logging.getLogger()
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def process_instr(trace):
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if trace.instr == "jal":
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# Spike jal format jal rd, -0xf -> jal rd, -15
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idx = trace.operand.rfind(",")
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imm = trace.operand[idx + 1:]
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if imm[0] == "-":
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imm = "-" + str(int(imm[1:], 16))
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else:
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imm = str(int(imm, 16))
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trace.operand = trace.operand[0:idx + 1] + imm
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# Properly format operands of all instructions of the form:
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# <instr> <reg1> <imm>(<reg2>)
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# The operands should be converted into CSV as:
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# "<reg1>,<reg2>,<imm>"
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m = ADDR_RE.search(trace.operand)
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if m:
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trace.operand = "{},{},{}".format(
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m.group("rd"), m.group("rs1"), m.group("imm"))
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def read_spike_instr(match, full_trace):
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"""Unpack a regex match for CORE_RE to a RiscvInstructionTraceEntry
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If full_trace is true, extract operand data from the disassembled
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instruction.
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"""
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# Extract the disassembled instruction.
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disasm = match.group('instr')
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# Spike's disassembler shows a relative jump as something like "j pc +
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# 0x123" or "j pc - 0x123". We just want the relative offset.
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disasm = disasm.replace('pc + ', '').replace('pc - ', '-')
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instr = RiscvInstructionTraceEntry()
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instr.pc = match.group('addr')
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instr.instr_str = disasm
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instr.binary = match.group('bin')
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if full_trace:
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opcode = disasm.split(' ')[0]
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operand = disasm[len(opcode):].replace(' ', '')
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instr.instr, instr.operand = \
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convert_pseudo_instr(opcode, operand, instr.binary)
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process_instr(instr)
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return instr
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def read_spike_trace(path, full_trace):
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"""Read a Spike simulation log at <path>, yielding executed instructions.
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This assumes that the log was generated with the -l and --log-commits options
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to Spike.
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If full_trace is true, extract operands from the disassembled instructions.
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Since Spike has a strange trampoline that always runs at the start, we skip
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instructions up to and including the one at PC 0x10010 (the end of the
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trampoline). At the end of a DV program, there's an ECALL instruction, which
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we take as a signal to stop checking, so we ditch everything that follows
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that instruction.
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This function yields instructions as it parses them as tuples of the form
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(entry, illegal). entry is a RiscvInstructionTraceEntry. illegal is a
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boolean, which is true if the instruction caused an illegal instruction trap.
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"""
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# This loop is a simple FSM with states TRAMPOLINE, INSTR, EFFECT. The idea
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# is that we're in state TRAMPOLINE until we get to the end of Spike's
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# trampoline, then we switch between INSTR (where we expect to read an
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# instruction) and EFFECT (where we expect to read commit information).
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#
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# We yield a RiscvInstructionTraceEntry object each time we leave EFFECT
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# (going back to INSTR), we loop back from INSTR to itself, or we get to the
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# end of the file and have an instruction in hand.
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#
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# On entry to the loop body, we are in state TRAMPOLINE if in_trampoline is
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# true. Otherwise, we are in state EFFECT if instr is not None, otherwise we
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# are in state INSTR.
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start_trampoline_re = re.compile(r'core.*: 0x0*10000 ')
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end_trampoline_re = re.compile(r'core.*: 0x0*10010 ')
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in_trampoline = False
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instr = None
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with open(path, 'r') as handle:
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for line in handle:
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if in_trampoline:
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# The TRAMPOLINE state
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if end_trampoline_re.match(line):
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in_trampoline = False
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continue
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elif start_trampoline_re.match(line):
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in_trampoline = True
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continue
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if instr is None:
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# The INSTR state. We expect to see a line matching CORE_RE.
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# We'll discard any other lines.
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instr_match = CORE_RE.match(line)
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if not instr_match:
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continue
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instr = read_spike_instr(instr_match, full_trace)
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# If instr.instr_str is 'ecall', we should stop.
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if instr.instr_str == 'ecall':
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break
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continue
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# The EFFECT state. If the line matches CORE_RE, we should have been in
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# state INSTR, so we yield the instruction we had, read the new
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# instruction and continue. As above, if the new instruction is 'ecall',
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# we need to stop immediately.
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instr_match = CORE_RE.match(line)
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if instr_match:
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yield instr, False
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instr = read_spike_instr(instr_match, full_trace)
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if instr.instr_str == 'ecall':
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break
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continue
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# The line doesn't match CORE_RE, so we are definitely on a follow-on
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# line in the log. First, check for illegal instructions
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if 'trap_illegal_instruction' in line:
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yield (instr, True)
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instr = None
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continue
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# The instruction seems to have been fine. Do we have commit data (from
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# the --log-commits Spike option)?
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commit_match = RD_RE.match(line)
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if commit_match:
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instr.gpr.append(gpr_to_abi(commit_match.group('reg')
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.replace(' ', '')) +
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':' + commit_match.group('val'))
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instr.mode = commit_match.group('pri')
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# At EOF, we might have an instruction in hand. Yield it if so.
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if instr is not None:
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yield (instr, False)
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def process_spike_sim_log(spike_log, csv, full_trace=0):
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"""Process SPIKE simulation log.
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Extract instruction and affected register information from spike simulation
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log and write the results to a CSV file at csv. Returns the number of
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instructions written.
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"""
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logging.info("Processing spike log : {}".format(spike_log))
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instrs_in = 0
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instrs_out = 0
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with open(csv, "w") as csv_fd:
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trace_csv = RiscvInstructionTraceCsv(csv_fd)
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trace_csv.start_new_trace()
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for (entry, illegal) in read_spike_trace(spike_log, full_trace):
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instrs_in += 1
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if illegal and full_trace:
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logging.debug("Illegal instruction: {}, opcode:{}"
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.format(entry.instr_str, entry.binary))
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# Instructions that cause no architectural update (which includes illegal
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# instructions) are ignored if full_trace is false.
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#
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# We say that an instruction caused an architectural update if either we
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# saw a commit line (in which case, entry.gpr will contain a single
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# entry) or the instruction was 'wfi' or 'ecall'.
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if not (full_trace or entry.gpr or entry.instr_str in ['wfi',
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'ecall']):
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continue
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trace_csv.write_trace_entry(entry)
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instrs_out += 1
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logging.info("Processed instruction count : {}".format(instrs_in))
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logging.info("CSV saved to : {}".format(csv))
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return instrs_out
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def main():
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# Parse input arguments
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parser = argparse.ArgumentParser()
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parser.add_argument("--log", type=str, help="Input spike simulation log")
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parser.add_argument("--csv", type=str, help="Output trace csv_buf file")
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parser.add_argument("-f", "--full_trace", dest="full_trace",
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action="store_true",
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help="Generate the full trace")
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parser.add_argument("-v", "--verbose", dest="verbose", action="store_true",
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help="Verbose logging")
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parser.set_defaults(full_trace=False)
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parser.set_defaults(verbose=False)
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args = parser.parse_args()
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setup_logging(args.verbose)
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# Process spike log
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process_spike_sim_log(args.log, args.csv, args.full_trace)
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if __name__ == "__main__":
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main()
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