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224 lines
11 KiB
Makefile
Executable file
224 lines
11 KiB
Makefile
Executable file
# Author: Florian Zaruba, ETH Zurich
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# Date: 03/19/2017
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# Description: Makefile for linting and testing Ariane.
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# compile everything in the following library
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library ?= work
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# Top level module to compile
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top_level ?= ariane_tb
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test_top_level ?= ariane_tb
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# Maximum amount of cycles for a successful simulation run
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max_cycles ?= 10000000
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# Test case to run
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test_case ?= core_test
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# QuestaSim Version
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questa_version ?= ${QUESTASIM_VERSION}
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# verilator version
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verilator ?= verilator
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# traget option
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target-options ?=
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# Sources
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# Package files -> compile first
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ariane_pkg := include/riscv_pkg.sv \
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src/debug/dm_pkg.sv \
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src/axi/src/axi_pkg.sv \
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include/ariane_pkg.sv \
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include/std_cache_pkg.sv \
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include/axi_if.sv
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# utility modules
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util := $(wildcard src/util/*.svh) \
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src/util/instruction_tracer_pkg.sv \
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src/util/instruction_tracer_if.sv \
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src/util/cluster_clock_gating.sv \
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src/util/sram.sv
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# Test packages
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test_pkg := $(wildcard tb/test/*/*sequence_pkg.sv*) \
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$(wildcard tb/test/*/*_pkg.sv*)
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# DPI
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dpi := $(patsubst tb/dpi/%.cc,work/%.o,$(wildcard tb/dpi/*.cc))
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dpi_hdr := $(wildcard tb/dpi/*.h)
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# this list contains the standalone components
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src := $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv)) \
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$(wildcard src/frontend/*.sv) \
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$(wildcard src/cache_subsystem/*.sv) \
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$(wildcard bootrom/*.sv) \
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$(wildcard src/axi_slice/*.sv) \
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$(wildcard src/clint/*.sv) \
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$(wildcard src/axi_node/src/*.sv) \
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$(wildcard src/axi_mem_if/src/*.sv) \
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$(filter-out src/debug/dm_pkg.sv, $(wildcard src/debug/*.sv)) \
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$(wildcard src/debug/debug_rom/*.sv) \
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src/fpga-support/rtl/SyncSpRamBeNx64.sv \
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src/common_cells/src/deprecated/generic_fifo.sv \
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src/common_cells/src/deprecated/pulp_sync.sv \
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src/common_cells/src/fifo_v2.sv \
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src/common_cells/src/lzc.sv \
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src/common_cells/src/rrarbiter.sv \
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src/common_cells/src/lfsr_8bit.sv \
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tb/ariane_testharness.sv \
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tb/common/SimDTM.sv \
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tb/common/SimJTAG.sv
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# look for testbenches
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tbs := tb/ariane_tb.sv tb/ariane_testharness.sv
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# RISCV asm tests and benchmark setup (used for CI)
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# there is a defined test-list with selected CI tests
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riscv-test-dir := tmp/riscv-tests/build/isa/
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riscv-benchmarks-dir := tmp/riscv-tests/build/benchmarks/
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riscv-asm-tests-list := ci/riscv-asm-tests.list
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riscv-benchmarks-list := ci/riscv-benchmarks.list
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riscv-asm-tests := $(shell xargs printf '\n%s' < $(riscv-asm-tests-list) | cut -b 1-)
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riscv-benchmarks := $(shell xargs printf '\n%s' < $(riscv-benchmarks-list) | cut -b 1-)
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# preset which runs a single test
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riscv-test ?= rv64ui-p-add
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# failed test directory
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failed-tests := $(wildcard failedtests/*.S)
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# Search here for include files (e.g.: non-standalone components)
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incdir := ./includes
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# Compile and sim flags
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compile_flag += +cover=bcfst+/dut -incr -64 -nologo -quiet -suppress 13262 -permissive
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uvm-flags += +UVM_NO_RELNOTES
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# Iterate over all include directories and write them with +incdir+ prefixed
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# +incdir+ works for Verilator and QuestaSim
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list_incdir := $(foreach dir, ${incdir}, +incdir+$(dir))
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# Build the TB and module using QuestaSim
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build: $(library) $(library)/.build-srcs $(library)/.build-tb $(library)/ariane_dpi.so
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# Optimize top level
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vopt$(questa_version) $(compile_flag) -work $(library) $(test_top_level) -o $(test_top_level)_optimized +acc -check_synthesis
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# src files
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$(library)/.build-srcs: $(ariane_pkg) $(util) $(src)
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vlog$(questa_version) $(compile_flag) -work $(library) $(filter %.sv,$(ariane_pkg)) $(list_incdir) -suppress 2583
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vlog$(questa_version) $(compile_flag) -work $(library) $(filter %.sv,$(util)) $(list_incdir) -suppress 2583
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# Suppress message that always_latch may not be checked thoroughly by QuestaSim.
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vlog$(questa_version) $(compile_flag) -work $(library) -pedanticerrors $(src) $(list_incdir) -suppress 2583
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touch $(library)/.build-srcs
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# build TBs
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$(library)/.build-tb: $(dpi) $(tbs)
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# Compile top level
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vlog$(questa_version) -sv $(tbs) -work $(library)
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touch $(library)/.build-tb
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# compile DPIs
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work/%.o: tb/dpi/%.cc $(dpi_hdr)
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$(CXX) -shared -fPIC -std=c++0x -Bsymbolic -I$(QUESTASIM_HOME)/include -o $@ $<
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$(library)/ariane_dpi.so: $(dpi)
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# Compile C-code and generate .so file
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g++ -shared -m64 -o $(library)/ariane_dpi.so $? -lfesvr
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$(library):
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# Create the library
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vlib${questa_version} ${library}
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# +jtag_rbb_enable=1
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sim: build $(library)/ariane_dpi.so
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vsim${questa_version} +permissive -64 -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
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+BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \
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$(QUESTASIM_FLAGS) \
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-gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi -do " do tb/wave/wave_core.do; run -all; exit" \
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${top_level}_optimized +permissive-off ++$(riscv-test-dir)/$(riscv-test) ++$(target-options)
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simc: build $(library)/ariane_dpi.so
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vsim${questa_version} +permissive -64 -c -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
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+BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \
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$(QUESTASIM_FLAGS) \
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-gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi -do " run -all; exit" \
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${top_level}_optimized +permissive-off ++$(riscv-test-dir)/$(riscv-test) ++$(target-options)
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$(riscv-asm-tests): build $(library)/ariane_dpi.so
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vsim${questa_version} +permissive -64 -c -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
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+BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \
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$(QUESTASIM_FLAGS) \
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-gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi \
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-do "coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" \
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${top_level}_optimized +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-asm-tests-$@.log
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$(riscv-benchmarks): build $(library)/ariane_dpi.so
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vsim${questa_version} +permissive -64 -c -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
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+BASEDIR=$(riscv-benchmarks-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \
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$(QUESTASIM_FLAGS) \
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-gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi \
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-do "coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" \
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${top_level}_optimized +permissive-off ++$(riscv-benchmarks-dir)/$@ ++$(target-options) | tee tmp/riscv-benchmarks-$@.log
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# can use -jX to run ci tests in parallel using X processes
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run-asm-tests: $(riscv-asm-tests)
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make check-asm-tests
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check-asm-tests:
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ci/check-tests.sh tmp/riscv-asm-tests- $(riscv-asm-tests-list)
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# can use -jX to run ci tests in parallel using X processes
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run-benchmarks: $(riscv-benchmarks)
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make check-benchmarks
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check-benchmarks:
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ci/check-tests.sh tmp/riscv-benchmarks- $(riscv-benchmarks-list)
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verilate_command := $(verilator) \
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$(ariane_pkg) \
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$(filter-out tb/ariane_bt.sv,$(src)) \
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src/util/sram.sv \
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+incdir+src/axi_node \
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--unroll-count 256 \
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-Werror-PINMISSING \
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-Werror-IMPLICIT \
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-Wno-fatal \
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-Wno-PINCONNECTEMPTY \
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-Wno-ASSIGNDLY \
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-Wno-DECLFILENAME \
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-Wno-UNOPTFLAT \
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-Wno-UNUSED \
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-Wno-style \
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-Wno-lint \
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$(if $(DEBUG),--trace-structs --trace,) \
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-LDFLAGS "-lfesvr" -CFLAGS "-std=c++11 -I../tb/dpi" -Wall --cc --vpi \
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$(list_incdir) --top-module ariane_testharness \
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--Mdir build -O3 \
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--exe tb/ariane_tb.cpp tb/dpi/SimDTM.cc tb/dpi/SimJTAG.cc tb/dpi/remote_bitbang.cc
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# User Verilator, at some point in the future this will be auto-generated
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verilate:
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$(verilate_command)
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cd build && make -j${NUM_JOBS} -f Variane_testharness.mk
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$(addsuffix -verilator,$(riscv-asm-tests)): verilate
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build/Variane_testharness $(riscv-test-dir)/$(subst -verilator,,$@)
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run-asm-tests-verilator: $(addsuffix -verilator, $(riscv-asm-tests))
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# split into two halfs for travis jobs (otherwise they will time out)
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run-asm-tests1-verilator: $(addsuffix -verilator, $(filter rv64ui-p-% ,$(riscv-asm-tests)))
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run-asm-tests2-verilator: $(addsuffix -verilator, $(filter rv64ui-v-% rv64um-%,$(riscv-asm-tests)))
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$(addsuffix -verilator,$(riscv-benchmarks)): verilate
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build/Variane_testharness $(riscv-benchmarks-dir)/$(subst -verilator,,$@)
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run-benchmarks-verilator: $(addsuffix -verilator,$(riscv-benchmarks))
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verify:
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qverify vlog -sv src/csr_regfile.sv
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clean:
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rm -rf work/ *.ucdb
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rm -rf build
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rm -f tmp/*.ucdb
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rm -f tmp/*.log
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rm -f *.wlf *vstf wlft*
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.PHONY:
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build lint build-moore $(riscv-asm-tests) $(addsuffix _verilator,$(riscv-asm-tests)) $(riscv-benchmarks) $(addsuffix _verilator,$(riscv-benchmarks)) check simc sim verilate clean verilate
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