mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-25 22:57:10 -04:00
a5f3184a65
* Add spike isa sim * Fix AMO problem in verilator * 🎨 Tidy up FPU wrapper * Bump axi_exclusive submodule * Refactor serpent AXI adapter, bump dbg and atomics submodules, add separate bootrom for linux on OpenPiton (#190) * Refactor serpent AXI adapter * Disable FPU in OpenPiton by default * Bump dbg and atomics submodules * Fix cache testbenches (interface change) * FPGA bootrom changes for OpenPiton SDHC * Introduce two bootroms, one for baremetal apps (pitonstream), and one for linux boot from SD * Testing barrier-based synchronisation instead of CLINT-based * This bootrom works for 2 core on g2 and if you change MAX_HARTS to 4, then 4 cores on vc707 * Add MAX_HARTS switch to makefile * Fix gitlab CI * Revert standard FPGA bootrom * Update Flist * Make UART_FREQ a parameter * Fix typo in tb.list and an error in define switch in ariane_pkg * Copy over SD-driver in bootloader from @leon575777642 * Fix compilation issues of bootrom * Change signal name in serpent periph portlist * Correct generate statement in serpent dcache memory * Add Piton SD Controller, FPGA fixes * Fix race condition in dcache misshandler * Add tandem spike to Make flow * Remove OpenPiton SD Card controller again
88 lines
3.8 KiB
Tcl
88 lines
3.8 KiB
Tcl
# Copyright 2018 ETH Zurich and University of Bologna.
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
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# hard-coded to Genesys 2 for the moment
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add_files -fileset constrs_1 -norecurse constraints/genesys-2.xdc
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read_ip xilinx/xlnx_mig_7_ddr3/ip/xlnx_mig_7_ddr3.xci
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read_ip xilinx/xlnx_axi_clock_converter/ip/xlnx_axi_clock_converter.xci
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read_ip xilinx/xlnx_axi_dwidth_converter/ip/xlnx_axi_dwidth_converter.xci
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read_ip xilinx/xlnx_axi_gpio/ip/xlnx_axi_gpio.xci
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read_ip xilinx/xlnx_axi_quad_spi/ip/xlnx_axi_quad_spi.xci
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read_ip xilinx/xlnx_clk_gen/ip/xlnx_clk_gen.xci
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# read_ip xilinx/xlnx_protocol_checker/ip/xlnx_protocol_checker.xci
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source scripts/add_sources.tcl
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set_property top ${project}_xilinx [current_fileset]
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if {$::env(BOARD) eq "genesys2"} {
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read_verilog -sv {src/genesysii.svh ../src/common_cells/include/common_cells/registers.svh}
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set file "src/genesysii.svh"
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set registers "../src/common_cells/include/common_cells/registers.svh"
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} else {
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exit 1
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}
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set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file" "*$registers"]]
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set_property -dict { file_type {Verilog Header} is_global_include 1} -objects $file_obj
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update_compile_order -fileset sources_1
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add_files -fileset constrs_1 -norecurse constraints/$project.xdc
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set_property include_dirs src/axi_sd_bridge/include [current_fileset]
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synth_design -rtl -name rtl_1
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set_property STEPS.SYNTH_DESIGN.ARGS.RETIMING true [get_runs synth_1]
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launch_runs synth_1
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wait_on_run synth_1
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open_run synth_1
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exec mkdir -p reports/
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exec rm -rf reports/*
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check_timing -verbose -file reports/$project.check_timing.rpt
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report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file reports/$project.timing_WORST_100.rpt
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report_timing -nworst 1 -delay_type max -sort_by group -file reports/$project.timing.rpt
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report_utilization -hierarchical -file reports/$project.utilization.rpt
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report_cdc -file reports/$project.cdc.rpt
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report_clock_interaction -file reports/$project.clock_interaction.rpt
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# set for RuntimeOptimized implementation
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set_property "steps.place_design.args.directive" "RuntimeOptimized" [get_runs impl_1]
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set_property "steps.route_design.args.directive" "RuntimeOptimized" [get_runs impl_1]
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launch_runs impl_1
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wait_on_run impl_1
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launch_runs impl_1 -to_step write_bitstream
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wait_on_run impl_1
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open_run impl_1
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# output Verilog netlist + SDC for timing simulation
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write_verilog -force -mode funcsim work-fpga/${project}_funcsim.v
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write_verilog -force -mode timesim work-fpga/${project}_timesim.v
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write_sdf -force work-fpga/${project}_timesim.sdf
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# reports
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exec mkdir -p reports/
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exec rm -rf reports/*
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check_timing -file reports/${project}.check_timing.rpt
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report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file reports/${project}.timing_WORST_100.rpt
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report_timing -nworst 1 -delay_type max -sort_by group -file reports/${project}.timing.rpt
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report_utilization -hierarchical -file reports/${project}.utilization.rpt
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