mirror of
https://github.com/openhwgroup/cva6.git
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167 lines
7 KiB
Python
Executable file
167 lines
7 KiB
Python
Executable file
# Copyright 2024 Thales DIS France SAS
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#
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# Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
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# you may not use this file except in compliance with the License.
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# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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# You may obtain a copy of the License at https://solderpad.org/licenses/
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#
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# Original Author: Jean-Roch COULON - Thales
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#!/usr/bin/python3
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import re
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from classes import Parameter
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from classes import PortIO
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from define_blacklist import define_blacklist
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from parameters_extractor import parameters_extractor
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from parameters_extractor import writeout_parameter_table
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if __name__ == "__main__":
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PATH = "04_cv32a65x"
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[spec_number, target] = PATH.split("_")
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print(spec_number, target)
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parameters = parameters_extractor(spec_number, target)
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pathout = f"./{spec_number}_{target}/design/source"
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fileout = f"{pathout}/parameters_{target}.rst"
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writeout_parameter_table(fileout, parameters, target)
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file = []
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file.append("../core/cva6.sv")
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file.append("../core/frontend/frontend.sv")
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file.append("../core/frontend/bht.sv")
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file.append("../core/frontend/btb.sv")
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file.append("../core/frontend/ras.sv")
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file.append("../core/frontend/instr_queue.sv")
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file.append("../core/frontend/instr_scan.sv")
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file.append("../core/instr_realign.sv")
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file.append("../core/id_stage.sv")
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file.append("../core/issue_stage.sv")
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file.append("../core/ex_stage.sv")
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file.append("../core/commit_stage.sv")
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file.append("../core/controller.sv")
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file.append("../core/csr_regfile.sv")
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file.append("../core/decoder.sv")
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file.append("../core/compressed_decoder.sv")
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file.append("../core/scoreboard.sv")
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file.append("../core/issue_read_operands.sv")
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file.append("../core/alu.sv")
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file.append("../core/branch_unit.sv")
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file.append("../core/csr_buffer.sv")
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file.append("../core/mult.sv")
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file.append("../core/multiplier.sv")
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file.append("../core/serdiv.sv")
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file.append("../core/load_store_unit.sv")
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file.append("../core/load_unit.sv")
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file.append("../core/store_unit.sv")
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file.append("../core/lsu_bypass.sv")
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file.append("../core/cvxif_fu.sv")
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file.append("../core/cache_subsystem/cva6_hpdcache_subsystem.sv")
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black_list = define_blacklist(parameters)
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for filein in file:
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comments = []
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a = re.match(r".*\/(.*).sv", filein)
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module = a.group(1)
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fileout = f"{pathout}/port_{module}.rst"
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print("Input file " + filein)
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print("Output file " + fileout)
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ports = []
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with open(filein, "r", encoding="utf-8") as fin:
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description = "none"
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connexion = "none"
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for line in fin:
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e = re.match(r"^ +(?:(in|out))put +([\S]*(?: +.* *|)) ([\S]*)\n", line)
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d = re.match(r"^ +\/\/ (.*) - ([\S]*)\n", line)
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if d:
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description = d.group(1)
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connexion = d.group(2)
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if e:
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name = e.group(3)
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name = name.replace(",", "")
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data_type = e.group(2)
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data_type = data_type.replace(" ", "")
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if connexion in black_list:
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for i, comment in enumerate(comments):
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if black_list[connexion][0] == comment[0]:
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comment[1] = (
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comment[1]
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+ f"\n| ``{name}`` {e.group(1)}put is tied to {black_list[connexion][1]}"
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)
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break
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else:
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comments.append(
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[
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black_list[connexion][0],
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f"``{name}`` {e.group(1)}put is tied to {black_list[connexion][1]}",
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]
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)
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else:
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if name in black_list:
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for i, comment in enumerate(comments):
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if black_list[name][0] == comment[0]:
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comment[1] = (
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comment[1]
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+ f"\n| ``{name}`` {e.group(1)}put is tied to {black_list[name][1]}"
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)
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break
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else:
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comments.append(
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[
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black_list[name][0],
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f"``{name}`` {e.group(1)}put is tied to {black_list[name][1]}",
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]
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)
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else:
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ports.append(
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PortIO(
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name, e.group(1), data_type, description, connexion
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)
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)
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description = "none"
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connexion = "none"
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with open(fileout, "w", encoding="utf-8") as fout:
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fout.write("..\n")
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fout.write(" Copyright 2024 Thales DIS France SAS\n")
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fout.write(
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' Licensed under the Solderpad Hardware License, Version 2.1 (the "License");\n'
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)
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fout.write(
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" you may not use this file except in compliance with the License.\n"
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)
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fout.write(" SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1\n")
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fout.write(
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" You may obtain a copy of the License at https://solderpad.org/licenses/\n\n"
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)
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fout.write(" Original Author: Jean-Roch COULON - Thales\n\n")
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fout.write(f".. _CVA6_{module}_ports:\n\n")
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fout.write(f".. list-table:: **{module} module** IO ports\n")
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fout.write(" :header-rows: 1\n")
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fout.write("\n")
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fout.write(" * - Signal\n")
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fout.write(" - IO\n")
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fout.write(" - Description\n")
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fout.write(" - connexion\n")
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fout.write(" - Type\n")
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for i, port in enumerate(ports):
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fout.write("\n")
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fout.write(f" * - ``{port.name}``\n")
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fout.write(f" - {port.direction}\n")
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fout.write(f" - {port.description}\n")
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fout.write(f" - {port.connexion}\n")
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fout.write(f" - {port.data_type}\n")
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fout.write("\n")
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if len(comments) != 0:
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fout.write(
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f"Due to {target} configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below\n"
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)
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fout.write("\n")
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for comment in comments:
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fout.write(f"| {comment[0]},\n| {comment[1]}\n")
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fout.write("\n")
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