mirror of
https://github.com/openhwgroup/cva6.git
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741e82133d
- Fix the AXI ID width for the CLINT (previously `4`, now `5`) - Parametrise the CLINT's AXI types - Deprecate `axi_[master|slave]_connect` and move to AXI assign macros, as they allow arbitrary AXI types Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
153 lines
4.8 KiB
Text
153 lines
4.8 KiB
Text
// Copyright (c) 2018 ETH Zurich, University of Bologna
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// All rights reserved.
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//
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// This code is under development and not yet released to the public.
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// Until it is released, the code is under the copyright of ETH Zurich and
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// the University of Bologna, and may contain confidential and/or unpublished
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// work. Any reuse/redistribution is strictly forbidden without written
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// permission from ETH Zurich.
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//
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// Bug fixes and contributions will eventually be released under the
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// SolderPad open hardware license in the context of the PULP platform
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// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the
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// University of Bologna.
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//
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// Author: Michael Schaffner <schaffner@iis.ee.ethz.ch>, ETH Zurich
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// Date: 15.08.2018
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// Description: File list for OpenPiton flow
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+incdir+src/common_cells/include/
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+incdir+src/util/
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include/riscv_pkg.sv
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src/riscv-dbg/src/dm_pkg.sv
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include/ariane_pkg.sv
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src/common_cells/src/deprecated/rrarbiter.sv
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src/common_cells/src/deprecated/fifo_v1.sv
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src/common_cells/src/deprecated/fifo_v2.sv
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src/common_cells/src/fifo_v3.sv
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src/common_cells/src/lfsr_8bit.sv
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src/common_cells/src/lzc.sv
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src/common_cells/src/rr_arb_tree.sv
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src/common_cells/src/rstgen_bypass.sv
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src/common_cells/src/cdc_2phase.sv
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src/common_cells/src/shift_reg.sv
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src/common_cells/src/unread.sv
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src/common_cells/src/popcount.sv
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src/common_cells/src/exp_backoff.sv
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src/register_interface/src/apb_to_reg.sv
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src/register_interface/src/reg_intf_pkg.sv
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src/register_interface/src/reg_intf.sv
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src/fpu/src/fpnew_pkg.sv
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src/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
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src/fpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv
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src/fpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv
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src/fpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv
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src/fpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv
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src/fpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv
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src/fpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv
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src/fpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv
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src/fpu/src/fpnew_cast_multi.sv
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src/fpu/src/fpnew_classifier.sv
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src/fpu/src/fpnew_divsqrt_multi.sv
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src/fpu/src/fpnew_fma_multi.sv
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src/fpu/src/fpnew_fma.sv
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src/fpu/src/fpnew_noncomp.sv
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src/fpu/src/fpnew_opgroup_block.sv
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src/fpu/src/fpnew_opgroup_fmt_slice.sv
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src/fpu/src/fpnew_opgroup_multifmt_slice.sv
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src/fpu/src/fpnew_rounding.sv
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src/fpu/src/fpnew_top.sv
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src/axi/src/axi_pkg.sv
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tb/ariane_soc_pkg.sv
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tb/ariane_axi_soc_pkg.sv
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include/ariane_axi_pkg.sv
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include/wt_cache_pkg.sv
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include/std_cache_pkg.sv
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include/axi_intf.sv
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include/instr_tracer_pkg.sv
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src/util/instr_tracer_if.sv
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src/util/instr_tracer.sv
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src/util/sram.sv
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src/fpga-support/rtl/SyncSpRamBeNx64.sv
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src/dromajo_ram.sv
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src/axi_mem_if/src/axi2mem.sv
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src/tech_cells_generic/src/pulp_clock_gating.sv
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src/tech_cells_generic/src/cluster_clock_inverter.sv
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src/tech_cells_generic/src/pulp_clock_mux2.sv
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src/pmp/src/pmp.sv
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src/pmp/src/pmp_entry.sv
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src/axi_adapter.sv
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src/alu.sv
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src/fpu_wrap.sv
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src/ariane.sv
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src/branch_unit.sv
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src/compressed_decoder.sv
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src/controller.sv
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src/csr_buffer.sv
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src/csr_regfile.sv
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src/decoder.sv
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src/ex_stage.sv
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src/instr_realign.sv
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src/frontend/btb.sv
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src/frontend/bht.sv
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src/frontend/ras.sv
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src/frontend/instr_scan.sv
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src/frontend/instr_queue.sv
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src/frontend/frontend.sv
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src/id_stage.sv
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src/issue_read_operands.sv
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src/issue_stage.sv
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src/load_unit.sv
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src/load_store_unit.sv
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src/mmu_sv39/mmu.sv
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src/mmu_sv32/cva6_mmu_sv32.sv
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src/mult.sv
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src/multiplier.sv
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src/serdiv.sv
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src/perf_counters.sv
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src/ptw.sv
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src/ariane_regfile_ff.sv
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src/re_name.sv
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src/scoreboard.sv
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src/store_buffer.sv
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src/amo_buffer.sv
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src/store_unit.sv
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src/tlb.sv
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src/commit_stage.sv
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src/cache_subsystem/wt_dcache_ctrl.sv
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src/cache_subsystem/wt_dcache_mem.sv
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src/cache_subsystem/wt_dcache_missunit.sv
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src/cache_subsystem/wt_dcache_wbuffer.sv
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src/cache_subsystem/wt_dcache.sv
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src/cache_subsystem/cva6_icache.sv
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src/cache_subsystem/wt_l15_adapter.sv
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src/cache_subsystem/wt_cache_subsystem.sv
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src/clint/clint.sv
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src/clint/axi_lite_interface.sv
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src/riscv-dbg/src/dm_csrs.sv
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src/riscv-dbg/src/dm_mem.sv
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src/riscv-dbg/src/dm_top.sv
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src/riscv-dbg/src/dmi_cdc.sv
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src/riscv-dbg/src/dmi_jtag.sv
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src/riscv-dbg/src/dm_sba.sv
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src/riscv-dbg/src/dmi_jtag_tap.sv
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src/riscv-dbg/debug_rom/debug_rom.sv
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openpiton/ariane_verilog_wrap.sv
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openpiton/riscv_peripherals.sv
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openpiton/bootrom/baremetal/bootrom.sv
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openpiton/bootrom/linux/bootrom_linux.sv
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src/rv_plic/rtl/rv_plic_target.sv
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src/rv_plic/rtl/rv_plic_gateway.sv
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src/rv_plic/rtl/plic_regmap.sv
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src/rv_plic/rtl/plic_top.sv
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fpga/src/axi2apb/src/axi2apb_wrap.sv
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fpga/src/axi2apb/src/axi2apb.sv
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fpga/src/axi2apb/src/axi2apb_64_32.sv
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fpga/src/axi_slice/src/axi_w_buffer.sv
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fpga/src/axi_slice/src/axi_b_buffer.sv
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fpga/src/axi_slice/src/axi_slice_wrap.sv
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fpga/src/axi_slice/src/axi_slice.sv
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fpga/src/axi_slice/src/axi_single_slice.sv
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fpga/src/axi_slice/src/axi_ar_buffer.sv
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fpga/src/axi_slice/src/axi_r_buffer.sv
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fpga/src/axi_slice/src/axi_aw_buffer.sv
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