mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-19 03:44:46 -04:00
741e82133d
- Fix the AXI ID width for the CLINT (previously `4`, now `5`) - Parametrise the CLINT's AXI types - Deprecate `axi_[master|slave]_connect` and move to AXI assign macros, as they allow arbitrary AXI types Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
801 lines
41 KiB
Makefile
801 lines
41 KiB
Makefile
# Author: Florian Zaruba, ETH Zurich
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# Date: 03/19/2017
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# Description: Makefile for linting and testing Ariane.
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# questa library
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library ?= work
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# verilator lib
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ver-library ?= work-ver
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# vcs lib
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vcs-library ?= work-vcs
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# library for DPI
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dpi-library ?= work-dpi
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# Top level module to compile
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top_level ?= ariane_tb
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# Maximum amount of cycles for a successful simulation run
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max_cycles ?= 10000000
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# Test case to run
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test_case ?= core_test
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# QuestaSim Version
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questa_version ?= ${QUESTASIM_VERSION}
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VLOG ?= vlog$(questa_version)
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VSIM ?= vsim$(questa_version)
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VOPT ?= vopt$(questa_version)
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VCOM ?= vcom$(questa_version)
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VLIB ?= vlib$(questa_version)
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VMAP ?= vmap$(questa_version)
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# verilator version
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verilator ?= verilator
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# traget option
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target-options ?=
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# additional definess
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defines ?= WT_DCACHE+RVFI_TRACE
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# test name for torture runs (binary name)
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test-location ?= output/test
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# set to either nothing or -log
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torture-logs :=
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# custom elf bin to run with sim or sim-verilator
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elf-bin ?= tmp/riscv-tests/build/benchmarks/dhrystone.riscv
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# board name for bitstream generation. Currently supported: kc705, genesys2
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BOARD ?= genesys2
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# root path
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mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST)))
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root-dir := $(dir $(mkfile_path))
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support_verilator_4 := $(shell ($(verilator) --version | grep '4\.') > /dev/null 2>&1 ; echo $$?)
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ifeq ($(support_verilator_4), 0)
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verilator_threads := 1
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endif
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ifndef RISCV
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$(error RISCV not set - please point your RISCV variable to your RISCV installation)
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endif
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# By default assume spike resides at the RISCV prefix.
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SPIKE_ROOT ?= $(RISCV)
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# setting additional xilinx board parameters for the selected board
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ifeq ($(BOARD), genesys2)
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XILINX_PART := xc7k325tffg900-2
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XILINX_BOARD := digilentinc.com:genesys2:part0:1.1
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CLK_PERIOD_NS := 20
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else ifeq ($(BOARD), kc705)
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XILINX_PART := xc7k325tffg900-2
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XILINX_BOARD := xilinx.com:kc705:part0:1.5
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CLK_PERIOD_NS := 20
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else ifeq ($(BOARD), vc707)
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XILINX_PART := xc7vx485tffg1761-2
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XILINX_BOARD := xilinx.com:vc707:part0:1.3
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CLK_PERIOD_NS := 20
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else
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$(error Unknown board - please specify a supported FPGA board)
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endif
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# spike tandem verification
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ifdef spike-tandem
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compile_flag += -define SPIKE_TANDEM
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ifndef preload
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$(error Tandem verification requires preloading)
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endif
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endif
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# target takes one of the following cva6 hardware configuration:
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# cv64a6_imafdc_sv39, cv32a6_imac_sv0, cv32a6_imac_sv32, cv32a6_imafc_sv32
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target ?= cv64a6_imafdc_sv39
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# Sources
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# Package files -> compile first
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ariane_pkg := core/include/$(target)_config_pkg.sv
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ariane_pkg += core/include/riscv_pkg.sv \
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corev_apu/riscv-dbg/src/dm_pkg.sv \
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core/include/ariane_pkg.sv \
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core/include/ariane_rvfi_pkg.sv \
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core/include/std_cache_pkg.sv \
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core/include/wt_cache_pkg.sv \
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core/include/cvxif_pkg.sv \
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corev_apu/axi/src/axi_pkg.sv \
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corev_apu/register_interface/src/reg_intf.sv \
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corev_apu/register_interface/src/reg_intf_pkg.sv \
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core/include/axi_intf.sv \
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corev_apu/tb/rvfi_pkg.sv \
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corev_apu/tb/ariane_soc_pkg.sv \
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corev_apu/tb/ariane_axi_soc_pkg.sv \
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core/include/ariane_axi_pkg.sv \
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core/fpu/src/fpnew_pkg.sv \
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core/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
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ariane_pkg := $(addprefix $(root-dir), $(ariane_pkg))
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# utility modules
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util := core/include/instr_tracer_pkg.sv \
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common/local/util/instr_tracer_if.sv \
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common/local/util/instr_tracer.sv \
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corev_apu/src/tech_cells_generic/src/cluster_clock_gating.sv \
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corev_apu/tb/common/mock_uart.sv \
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common/local/util/sram.sv
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ifdef spike-tandem
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util += tb/common/spike.sv
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endif
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util := $(addprefix $(root-dir), $(util))
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# Test packages
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test_pkg := $(wildcard tb/test/*/*sequence_pkg.sv*) \
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$(wildcard tb/test/*/*_pkg.sv*)
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# DPI
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dpi := $(patsubst corev_apu/tb/dpi/%.cc, ${dpi-library}/%.o, $(wildcard corev_apu/tb/dpi/*.cc))
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# filter spike stuff if tandem is not activated
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ifndef spike-tandem
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dpi := $(filter-out ${dpi-library}/spike.o ${dpi-library}/sim_spike.o, $(dpi))
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endif
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# filter dromajo stuff if dromajo is not activated
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ifndef DROMAJO
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dpi := $(filter-out ${dpi-library}/dromajo_cosim_dpi.o, $(dpi))
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endif
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dpi_hdr := $(wildcard corev_apu/tb/dpi/*.h)
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dpi_hdr := $(addprefix $(root-dir), $(dpi_hdr))
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CFLAGS := -I$(QUESTASIM_HOME)/include \
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-I$(VCS_HOME)/include \
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-I$(RISCV)/include \
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-I$(SPIKE_ROOT)/include \
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$(if $(DROMAJO), -I../corev_apu/tb/dromajo/src,) \
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-std=c++11 -I../corev_apu/tb/dpi -O3
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ifdef XCELIUM_HOME
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CFLAGS += -I$(XCELIUM_HOME)/tools/include
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else
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$(warning XCELIUM_HOME not set which is necessary for compiling DPIs when using XCELIUM)
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endif
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ifdef spike-tandem
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CFLAGS += -Itb/riscv-isa-sim/install/include/spike
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endif
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# this list contains the standalone components
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src := $(filter-out core/ariane_regfile.sv, $(wildcard core/*.sv)) \
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$(filter-out core/fpu/src/fpnew_pkg.sv, $(wildcard core/fpu/src/*.sv)) \
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$(filter-out core/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv, \
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$(wildcard core/fpu/src/fpu_div_sqrt_mvp/hdl/*.sv)) \
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$(wildcard core/frontend/*.sv) \
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$(filter-out core/cache_subsystem/std_no_dcache.sv, \
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$(wildcard core/cache_subsystem/*.sv)) \
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$(wildcard corev_apu/bootrom/*.sv) \
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$(wildcard corev_apu/clint/*.sv) \
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$(wildcard corev_apu/fpga/src/axi2apb/src/*.sv) \
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$(wildcard corev_apu/fpga/src/apb_timer/*.sv) \
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$(wildcard corev_apu/fpga/src/axi_slice/src/*.sv) \
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$(wildcard corev_apu/src/axi_riscv_atomics/src/*.sv) \
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$(wildcard corev_apu/axi_mem_if/src/*.sv) \
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$(wildcard core/pmp/src/*.sv) \
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corev_apu/rv_plic/rtl/rv_plic_target.sv \
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corev_apu/rv_plic/rtl/rv_plic_gateway.sv \
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corev_apu/rv_plic/rtl/plic_regmap.sv \
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corev_apu/rv_plic/rtl/plic_top.sv \
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corev_apu/riscv-dbg/src/dmi_cdc.sv \
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corev_apu/riscv-dbg/src/dmi_jtag.sv \
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corev_apu/riscv-dbg/src/dmi_jtag_tap.sv \
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corev_apu/riscv-dbg/src/dm_csrs.sv \
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corev_apu/riscv-dbg/src/dm_mem.sv \
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corev_apu/riscv-dbg/src/dm_sba.sv \
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corev_apu/riscv-dbg/src/dm_top.sv \
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corev_apu/riscv-dbg/debug_rom/debug_rom.sv \
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corev_apu/register_interface/src/apb_to_reg.sv \
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corev_apu/axi/src/axi_multicut.sv \
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common/submodules/common_cells/src/cf_math_pkg.sv \
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common/submodules/common_cells/src/deprecated/generic_fifo.sv \
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common/submodules/common_cells/src/deprecated/pulp_sync.sv \
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common/submodules/common_cells/src/deprecated/find_first_one.sv \
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common/submodules/common_cells/src/rstgen_bypass.sv \
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common/submodules/common_cells/src/rstgen.sv \
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common/submodules/common_cells/src/stream_mux.sv \
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common/submodules/common_cells/src/stream_demux.sv \
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common/submodules/common_cells/src/exp_backoff.sv \
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common/submodules/common_cells/src/addr_decode.sv \
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common/submodules/common_cells/src/stream_register.sv \
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corev_apu/axi/src/axi_cut.sv \
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corev_apu/axi/src/axi_join.sv \
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corev_apu/axi/src/axi_delayer.sv \
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corev_apu/axi/src/axi_to_axi_lite.sv \
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corev_apu/axi/src/axi_id_prepend.sv \
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corev_apu/axi/src/axi_atop_filter.sv \
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corev_apu/axi/src/axi_err_slv.sv \
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corev_apu/axi/src/axi_mux.sv \
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corev_apu/axi/src/axi_demux.sv \
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corev_apu/axi/src/axi_xbar.sv \
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corev_apu/fpga-support/rtl/SyncSpRamBeNx64.sv \
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common/submodules/common_cells/src/unread.sv \
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common/submodules/common_cells/src/sync.sv \
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common/submodules/common_cells/src/cdc_2phase.sv \
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common/submodules/common_cells/src/spill_register_flushable.sv \
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common/submodules/common_cells/src/spill_register.sv \
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common/submodules/common_cells/src/sync_wedge.sv \
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common/submodules/common_cells/src/edge_detect.sv \
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common/submodules/common_cells/src/stream_arbiter.sv \
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common/submodules/common_cells/src/stream_arbiter_flushable.sv \
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common/submodules/common_cells/src/deprecated/fifo_v1.sv \
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common/submodules/common_cells/src/deprecated/fifo_v2.sv \
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common/submodules/common_cells/src/fifo_v3.sv \
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common/submodules/common_cells/src/lzc.sv \
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common/submodules/common_cells/src/popcount.sv \
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common/submodules/common_cells/src/rr_arb_tree.sv \
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common/submodules/common_cells/src/deprecated/rrarbiter.sv \
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common/submodules/common_cells/src/stream_delay.sv \
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common/submodules/common_cells/src/lfsr.sv \
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common/submodules/common_cells/src/lfsr_8bit.sv \
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common/submodules/common_cells/src/lfsr_16bit.sv \
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common/submodules/common_cells/src/delta_counter.sv \
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common/submodules/common_cells/src/counter.sv \
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common/submodules/common_cells/src/shift_reg.sv \
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corev_apu/src/tech_cells_generic/src/pulp_clock_gating.sv \
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corev_apu/src/tech_cells_generic/src/cluster_clock_inverter.sv \
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corev_apu/src/tech_cells_generic/src/pulp_clock_mux2.sv \
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corev_apu/tb/ariane_testharness.sv \
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corev_apu/tb/ariane_peripherals.sv \
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corev_apu/tb/rvfi_tracer.sv \
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corev_apu/tb/common/uart.sv \
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corev_apu/tb/common/SimDTM.sv \
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corev_apu/tb/common/SimJTAG.sv
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# SV32 MMU for CV32, SV39 MMU for CV64
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ifeq ($(findstring 32, $(target)),32)
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src += $(wildcard core/mmu_sv32/*.sv)
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else
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src += $(wildcard core/mmu_sv39/*.sv)
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endif
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src := $(addprefix $(root-dir), $(src))
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copro_src := core/cvxif_example/include/cvxif_instr_pkg.sv \
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$(wildcard core/cvxif_example/*.sv)
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copro_src := $(addprefix $(root-dir), $(copro_src))
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uart_src := $(wildcard corev_apu/fpga/src/apb_uart/src/*.vhd)
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uart_src := $(addprefix $(root-dir), $(uart_src))
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fpga_src := $(wildcard corev_apu/fpga/src/*.sv) $(wildcard corev_apu/fpga/src/bootrom/*.sv) $(wildcard corev_apu/fpga/src/ariane-ethernet/*.sv)
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fpga_src := $(addprefix $(root-dir), $(fpga_src))
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# look for testbenches
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tbs := corev_apu/tb/ariane_tb.sv corev_apu/tb/ariane_testharness.sv
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tbs := $(addprefix $(root-dir), $(tbs))
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# RISCV asm tests and benchmark setup (used for CI)
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# there is a definesd test-list with selected CI tests
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riscv-test-dir := tmp/riscv-tests/build/isa/
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riscv-benchmarks-dir := tmp/riscv-tests/build/benchmarks/
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riscv-asm-tests-list := ci/riscv-asm-tests.list
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riscv-amo-tests-list := ci/riscv-amo-tests.list
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riscv-mul-tests-list := ci/riscv-mul-tests.list
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riscv-fp-tests-list := ci/riscv-fp-tests.list
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riscv-benchmarks-list := ci/riscv-benchmarks.list
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riscv-asm-tests := $(shell xargs printf '\n%s' < $(riscv-asm-tests-list) | cut -b 1-)
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riscv-amo-tests := $(shell xargs printf '\n%s' < $(riscv-amo-tests-list) | cut -b 1-)
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riscv-mul-tests := $(shell xargs printf '\n%s' < $(riscv-mul-tests-list) | cut -b 1-)
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riscv-fp-tests := $(shell xargs printf '\n%s' < $(riscv-fp-tests-list) | cut -b 1-)
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riscv-benchmarks := $(shell xargs printf '\n%s' < $(riscv-benchmarks-list) | cut -b 1-)
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# Search here for include files (e.g.: non-standalone components)
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incdir := common/submodules/common_cells/include/ corev_apu/axi/include/
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# Compile and sim flags
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compile_flag += +cover=bcfst+/dut -incr -64 -nologo -quiet -suppress 13262 -permissive +define+$(defines)
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uvm-flags += +UVM_NO_RELNOTES +UVM_VERBOSITY=LOW
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questa-flags += -t 1ns -64 -coverage -classdebug $(gui-sim) $(QUESTASIM_FLAGS)
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compile_flag_vhd += -64 -nologo -quiet -2008
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# Iterate over all include directories and write them with +incdir+ prefixed
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# +incdir+ works for Verilator and QuestaSim
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list_incdir := $(foreach dir, ${incdir}, +incdir+$(dir))
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# RISCV torture setup
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riscv-torture-dir := tmp/riscv-torture
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# old java flags -Xmx1G -Xss8M -XX:MaxPermSize=128M
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# -XshowSettings -Xdiag
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riscv-torture-bin := java -jar sbt-launch.jar
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# if defined, calls the questa targets in batch mode
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ifdef batch-mode
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questa-flags += -c
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questa-cmd := -do "coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]"
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questa-cmd += -do " log -r /*; run -all;"
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else
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questa-cmd := -do " log -r /*; run -all;"
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endif
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# we want to preload the memories
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ifdef preload
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questa-cmd += +PRELOAD=$(preload)
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elf-bin = none
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endif
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ifdef spike-tandem
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questa-cmd += -gblso tb/riscv-isa-sim/install/lib/libriscv.so
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endif
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# remote bitbang is enabled
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ifdef rbb
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questa-cmd += +jtag_rbb_enable=1
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else
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questa-cmd += +jtag_rbb_enable=0
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endif
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vcs_build: $(dpi-library)/ariane_dpi.so
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mkdir -p $(vcs-library)
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cd $(vcs-library) &&\
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vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog -ntb_opts uvm-1.2 &&\
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vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog -ntb_opts uvm-1.2 +define+$(defines) $(filter %.sv,$(ariane_pkg)) +incdir+core/include/+$(VCS_HOME)/etc/uvm-1.2/dpi &&\
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vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog -ntb_opts uvm-1.2 +define+$(defines) $(filter %.sv,$(util)) +incdir+../common/local/util+../core/include/+src/util/+$(VCS_HOME)/etc/uvm-1.2/dpi &&\
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vhdlan $(if $(VERDI), -kdb,) -full64 -nc $(filter %.vhd,$(uart_src)) &&\
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vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog -ntb_opts uvm-1.2 $(filter %.sv,$(copro_src)) &&\
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vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog -ntb_opts uvm-1.2 -assert svaext +define+$(defines) $(filter %.sv,$(src)) +incdir+../core/include/+../common/submodules/common_cells/include/+../common/local/util/+../corev_apu/axi/include/+$(VCS_HOME)/etc/uvm-1.2/dpi &&\
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vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog -ntb_opts uvm-1.2 $(tbs) +define+$(defines) +incdir+../corev_apu/axi/include/ &&\
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vcs $(if $(VERDI), -kdb -debug_access+all -lca,) -full64 -timescale=1ns/1ns -ntb_opts uvm-1.2 work.ariane_tb
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vcs: vcs_build
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cd $(vcs-library) && ./simv $(if $(VERDI), -verdi,) +permissive -sv_lib ../work-dpi/ariane_dpi +PRELOAD=$(elf-bin) +permissive-off ++$(elf-bin)| tee vcs.log
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# Build the TB and module using QuestaSim
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build: $(library) $(library)/.build-srcs $(library)/.build-tb $(dpi-library)/ariane_dpi.so
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# Optimize top level
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$(VOPT) $(compile_flag) -work $(library) $(top_level) -o $(top_level)_optimized +acc -check_synthesis
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# src files
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$(library)/.build-srcs: $(util) $(library)
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$(VLOG) $(compile_flag) -work $(library) $(filter %.sv,$(ariane_pkg)) $(list_incdir) -suppress 2583
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# $(VCOM) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(ariane_pkg))
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$(VLOG) $(compile_flag) -timescale "1ns / 1ns" -work $(library) $(filter %.sv,$(util)) $(list_incdir) -suppress 2583
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# Suppress message that always_latch may not be checked thoroughly by QuestaSim.
|
|
$(VCOM) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(uart_src))
|
|
# $(VCOM) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(src))
|
|
$(VLOG) $(compile_flag) -timescale "1ns / 1ns" -work $(library) -pedanticerrors $(filter %.sv,$(src)) $(list_incdir) -suppress 2583
|
|
touch $(library)/.build-srcs
|
|
|
|
# build TBs
|
|
$(library)/.build-tb: $(dpi)
|
|
# Compile top level
|
|
$(VLOG) $(compile_flag) -timescale "1ns / 1ns" -sv $(tbs) -work $(library) $(list_incdir)
|
|
touch $(library)/.build-tb
|
|
|
|
$(library):
|
|
$(VLIB) $(library)
|
|
|
|
# compile DPIs
|
|
$(dpi-library)/%.o: corev_apu/tb/dpi/%.cc $(dpi_hdr)
|
|
mkdir -p $(dpi-library)
|
|
$(CXX) -shared -fPIC -std=c++0x -Bsymbolic $(CFLAGS) -c $< -o $@
|
|
|
|
$(dpi-library)/ariane_dpi.so: $(dpi)
|
|
mkdir -p $(dpi-library)
|
|
# Compile C-code and generate .so file
|
|
$(CXX) -shared -m64 -o $(dpi-library)/ariane_dpi.so $? -L$(RISCV)/lib -L$(SPIKE_ROOT)/lib -Wl,-rpath,$(RISCV)/lib -Wl,-rpath,$(SPIKE_ROOT)/lib -lfesvr
|
|
|
|
# single test runs on Questa can be started by calling make <testname>, e.g. make towers.riscv
|
|
# the test names are defined in ci/riscv-asm-tests.list, and in ci/riscv-benchmarks.list
|
|
# if you want to run in batch mode, use make <testname> batch-mode=1
|
|
# alternatively you can call make sim elf-bin=<path/to/elf-bin> in order to load an arbitrary binary
|
|
generate-trace-vsim:
|
|
make sim preload=$(preload) elf-bin= batch-mode=1
|
|
make generate-trace
|
|
|
|
sim: build
|
|
$(VSIM) +permissive $(questa-flags) $(questa-cmd) -lib $(library) +MAX_CYCLES=$(max_cycles) +UVM_TESTNAME=$(test_case) \
|
|
+BASEDIR=$(riscv-test-dir) $(uvm-flags) $(QUESTASIM_FLAGS) -gblso $(SPIKE_ROOT)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
|
|
${top_level}_optimized +permissive-off ++$(elf-bin) ++$(target-options) | tee sim.log
|
|
|
|
$(riscv-asm-tests): build
|
|
$(VSIM) +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \
|
|
+BASEDIR=$(riscv-test-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(SPIKE_ROOT)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
|
|
${top_level}_optimized $(QUESTASIM_FLAGS) +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-asm-tests-$@.log
|
|
|
|
$(riscv-amo-tests): build
|
|
$(VSIM) +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \
|
|
+BASEDIR=$(riscv-test-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(SPIKE_ROOT)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
|
|
${top_level}_optimized $(QUESTASIM_FLAGS) +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-amo-tests-$@.log
|
|
|
|
$(riscv-mul-tests): build
|
|
$(VSIM) +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \
|
|
+BASEDIR=$(riscv-test-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(SPIKE_ROOT)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
|
|
${top_level}_optimized $(QUESTASIM_FLAGS) +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-mul-tests-$@.log
|
|
|
|
$(riscv-fp-tests): build
|
|
$(VSIM) +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \
|
|
+BASEDIR=$(riscv-test-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(SPIKE_ROOT)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
|
|
${top_level}_optimized $(QUESTASIM_FLAGS) +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-fp-tests-$@.log
|
|
|
|
$(riscv-benchmarks): build
|
|
$(VSIM) +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \
|
|
+BASEDIR=$(riscv-benchmarks-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(SPIKE_ROOT)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
|
|
${top_level}_optimized $(QUESTASIM_FLAGS) +permissive-off ++$(riscv-benchmarks-dir)/$@ ++$(target-options) | tee tmp/riscv-benchmarks-$@.log
|
|
|
|
# can use -jX to run ci tests in parallel using X processes
|
|
run-asm-tests: $(riscv-asm-tests)
|
|
$(MAKE) check-asm-tests
|
|
|
|
run-amo-tests: $(riscv-amo-tests)
|
|
$(MAKE) check-amo-tests
|
|
|
|
run-mul-tests: $(riscv-mul-tests)
|
|
$(MAKE) check-mul-tests
|
|
|
|
run-fp-tests: $(riscv-fp-tests)
|
|
$(MAKE) check-fp-tests
|
|
|
|
check-asm-tests:
|
|
ci/check-tests.sh tmp/riscv-asm-tests- $(shell wc -l $(riscv-asm-tests-list) | awk -F " " '{ print $1 }')
|
|
|
|
check-amo-tests:
|
|
ci/check-tests.sh tmp/riscv-amo-tests- $(shell wc -l $(riscv-amo-tests-list) | awk -F " " '{ print $1 }')
|
|
|
|
check-mul-tests:
|
|
ci/check-tests.sh tmp/riscv-mul-tests- $(shell wc -l $(riscv-mul-tests-list) | awk -F " " '{ print $1 }')
|
|
|
|
check-fp-tests:
|
|
ci/check-tests.sh tmp/riscv-fp-tests- $(shell wc -l $(riscv-fp-tests-list) | awk -F " " '{ print $1 }')
|
|
|
|
# can use -jX to run ci tests in parallel using X processes
|
|
run-benchmarks: $(riscv-benchmarks)
|
|
$(MAKE) check-benchmarks
|
|
|
|
check-benchmarks:
|
|
ci/check-tests.sh tmp/riscv-benchmarks- $(shell wc -l $(riscv-benchmarks-list) | awk -F " " '{ print $1 }')
|
|
#####################################
|
|
# xrun-specific commands, variables
|
|
#####################################
|
|
XRUN ?= xrun
|
|
XRUN_WORK_DIR ?= xrun_work
|
|
XRUN_RESULTS_DIR ?= xrun_results
|
|
XRUN_UVMHOME_ARG ?= CDNS-1.2-ML
|
|
XRUN_COMPL_LOG ?= xrun_compl.log
|
|
XRUN_RUN_LOG ?= xrun_run.log
|
|
CVA6_HOME ?= $(realpath -s $(root-dir))
|
|
|
|
XRUN_INCDIR :=+incdir+$(CVA6_HOME)/src/axi_node \
|
|
+incdir+$(CVA6_HOME)/src/common_cells/include \
|
|
+incdir+$(CVA6_HOME)/src/util
|
|
XRUN_TB := $(addprefix $(CVA6_HOME)/, corev_apu/tb/ariane_tb.sv)
|
|
|
|
XRUN_COMP_FLAGS ?= -64bit -disable_sem2009 -access +rwc \
|
|
-sv -v93 -uvm -uvmhome $(XRUN_UVMHOME_ARG) \
|
|
-sv_lib $(CVA6_HOME)/$(dpi-library)/ariane_dpi.so \
|
|
-smartorder -sv -top worklib.$(top_level) \
|
|
-xceligen on=1903 +define+$(defines) -timescale 1ns/1ps \
|
|
|
|
XRUN_RUN_FLAGS := -R -64bit -disable_sem2009 -access +rwc -timescale 1ns/1ps \
|
|
-sv_lib $(CVA6_HOME)/$(dpi-library)/ariane_dpi.so -xceligen on=1903 \
|
|
|
|
XRUN_DISABLED_WARNINGS := BIGWIX \
|
|
ZROMCW \
|
|
STRINT \
|
|
ENUMERR \
|
|
SPDUSD \
|
|
RNDXCELON
|
|
|
|
XRUN_DISABLED_WARNINGS := $(patsubst %, -nowarn %, $(XRUN_DISABLED_WARNINGS))
|
|
|
|
XRUN_COMP = $(XRUN_COMP_FLAGS) \
|
|
$(XRUN_DISABLED_WARNINGS) \
|
|
$(XRUN_INCDIR) \
|
|
$(filter %.sv, $(ariane_pkg)) \
|
|
$(filter %.sv, $(util)) \
|
|
$(filter %.vhd, $(uart_src)) \
|
|
$(filter %.sv, $(src)) \
|
|
$(filter %.sv, $(XRUN_TB)) \
|
|
|
|
XRUN_RUN = $(XRUN_RUN_FLAGS) \
|
|
$(XRUN_DISABLED_WARNINGS) \
|
|
|
|
xrun_clean:
|
|
@echo "[XRUN] clean up"
|
|
rm -rf $(XRUN_RESULTS_DIR)
|
|
rm -rf $(dpi-library)
|
|
|
|
xrun_comp: $(dpi-library)/ariane_dpi.so
|
|
@echo "[XRUN] Building Model"
|
|
mkdir -p $(XRUN_RESULTS_DIR)
|
|
cd $(XRUN_RESULTS_DIR) && $(XRUN) \
|
|
+permissive \
|
|
$(XRUN_COMP) \
|
|
-l $(XRUN_COMPL_LOG) \
|
|
+permissive-off \
|
|
-elaborate
|
|
|
|
xrun_sim: xrun_comp
|
|
@echo "[XRUN] Simulating selected binary"
|
|
cd $(XRUN_RESULTS_DIR) && $(XRUN) \
|
|
+permissive \
|
|
$(XRUN_RUN) \
|
|
+MAX_CYCLES=$(max_cycles) \
|
|
+UVM_TESTNAME=$(test_case) \
|
|
-l $(XRUN_RUN_LOG) \
|
|
+permissive-off \
|
|
++$(elf-bin)
|
|
|
|
#-e "set_severity_pack_assert_off {warning}; set_pack_assert_off {numeric_std}" TODO: This will remove assertion warning at the beginning of the simulation.
|
|
|
|
xrun_all: xrun_clean xrun_comp xrun_sim
|
|
|
|
$(addprefix xrun_, $(riscv-asm-tests)): xrun_comp
|
|
cd $(XRUN_RESULTS_DIR); \
|
|
mkdir -p isa/asm/; \
|
|
$(XRUN) +permissive $(XRUN_RUN) +MAX_CYCLES=$(max_cycles) +UVM_TESTNAME=$(test_case) \
|
|
-l isa/asm/$(notdir $@).log +permissive-off ++$(CVA6_HOME)/$(riscv-test-dir)/$(patsubst xrun_%,%,$@)
|
|
|
|
$(addprefix xrun_, $(riscv-amo-tests)): xrun_comp
|
|
cd $(XRUN_RESULTS_DIR); \
|
|
mkdir -p isa/amo/; \
|
|
$(XRUN) +permissive $(XRUN_RUN) +MAX_CYCLES=$(max_cycles) +UVM_TESTNAME=$(test_case) \
|
|
-l isa/amo/$(notdir $@).log +permissive-off ++$(CVA6_HOME)/$(riscv-test-dir)/$(patsubst xrun_%,%,$@)
|
|
|
|
$(addprefix xrun_, $(riscv-mul-tests)): xrun_comp
|
|
cd $(XRUN_RESULTS_DIR); \
|
|
mkdir -p isa/mul/; \
|
|
$(XRUN) +permissive $(XRUN_RUN) +MAX_CYCLES=$(max_cycles) +UVM_TESTNAME=$(test_case) \
|
|
-l isa/mul/$(notdir $@).log +permissive-off ++$(CVA6_HOME)/$(riscv-test-dir)/$(patsubst xrun_%,%,$@)
|
|
|
|
$(addprefix xrun_, $(riscv-fp-tests)): xrun_comp
|
|
cd $(XRUN_RESULTS_DIR); \
|
|
mkdir -p isa/fp/; \
|
|
$(XRUN) +permissive $(XRUN_RUN) +MAX_CYCLES=$(max_cycles) +UVM_TESTNAME=$(test_case) \
|
|
-l isa/fp/$(notdir $@).log +permissive-off ++$(CVA6_HOME)/$(riscv-test-dir)/$(patsubst xrun_%,%,$@)
|
|
|
|
$(addprefix xrun_, $(riscv-benchmarks)): xrun_comp
|
|
cd $(XRUN_RESULTS_DIR); \
|
|
mkdir -p benchmarks/; \
|
|
$(XRUN) +permissive $(XRUN_RUN) +MAX_CYCLES=$(max_cycles) +UVM_TESTNAME=$(test_case) \
|
|
-l benchmarks/$(notdir $@).log +permissive-off ++$(CVA6_HOME)/$(riscv-benchmarks-dir)/$(patsubst xrun_%,%,$@)
|
|
|
|
# can use -jX to run ci tests in parallel using X processes
|
|
xrun-asm-tests: $(addprefix xrun_, $(riscv-asm-tests))
|
|
$(MAKE) xrun-check-asm-tests
|
|
|
|
xrun-amo-tests: $(addprefix xrun_, $(riscv-amo-tests))
|
|
$(MAKE) xrun-check-amo-tests
|
|
|
|
xrun-mul-tests: $(addprefix xrun_, $(riscv-mul-tests))
|
|
$(MAKE) xrun-check-mul-tests
|
|
|
|
xrun-fp-tests: $(addprefix xrun_, $(riscv-fp-tests))
|
|
$(MAKE) xrun-check-fp-tests
|
|
|
|
xrun-check-asm-tests:
|
|
ci/check-tests.sh $(XRUN_RESULTS_DIR)/isa/asm/ $(shell wc -l $(riscv-asm-tests-list) | awk -F " " '{ print $1 }')
|
|
|
|
xrun-check-amo-tests:
|
|
ci/check-tests.sh $(XRUN_RESULTS_DIR)/isa/amo/ $(shell wc -l $(riscv-amo-tests-list) | awk -F " " '{ print $1 }')
|
|
|
|
xrun-check-mul-tests:
|
|
ci/check-tests.sh $(XRUN_RESULTS_DIR)/isa/mul/ $(shell wc -l $(riscv-mul-tests-list) | awk -F " " '{ print $1 }')
|
|
|
|
xrun-check-fp-tests:
|
|
ci/check-tests.sh $(XRUN_RESULTS_DIR)/isa/fp/ $(shell wc -l $(riscv-fp-tests-list) | awk -F " " '{ print $1 }')
|
|
|
|
|
|
# can use -jX to run ci tests in parallel using X processes
|
|
xrun-benchmarks: $(addprefix xrun_, $(riscv-benchmarks))
|
|
$(MAKE) check-benchmarks
|
|
|
|
|
|
xrun-check-benchmarks:
|
|
ci/check-tests.sh $(XRUN_RESULTS_DIR)/benchmarks/ $(shell wc -l $(riscv-benchmarks-list) | awk -F " " '{ print $1 }')
|
|
|
|
xrun-ci: xrun-asm-tests xrun-amo-tests xrun-mul-tests xrun-fp-tests xrun-benchmarks
|
|
|
|
# verilator-specific
|
|
verilate_command := $(verilator) \
|
|
$(filter-out %.vhd, $(ariane_pkg)) \
|
|
$(filter-out core/fpu_wrap.sv, $(filter-out %.vhd, $(src))) \
|
|
$(copro_src) \
|
|
+define+$(defines) \
|
|
common/local/util/sram.sv \
|
|
corev_apu/tb/common/mock_uart.sv \
|
|
+incdir+corev_apu/axi_node \
|
|
$(if $(verilator_threads), --threads $(verilator_threads)) \
|
|
--unroll-count 256 \
|
|
-Werror-PINMISSING \
|
|
-Werror-IMPLICIT \
|
|
-Wno-fatal \
|
|
-Wno-PINCONNECTEMPTY \
|
|
-Wno-ASSIGNDLY \
|
|
-Wno-DECLFILENAME \
|
|
-Wno-UNUSED \
|
|
-Wno-UNOPTFLAT \
|
|
-Wno-BLKANDNBLK \
|
|
-Wno-style \
|
|
$(if ($(PRELOAD)!=""), -DPRELOAD=1,) \
|
|
$(if $(DROMAJO), -DDROMAJO=1,) \
|
|
$(if $(PROFILE),--stats --stats-vars --profile-cfuncs,) \
|
|
$(if $(DEBUG),--trace --trace-structs,) \
|
|
-LDFLAGS "-L$(RISCV)/lib -L$(SPIKE_ROOT)/lib -Wl,-rpath,$(RISCV)/lib -Wl,-rpath,$(SPIKE_ROOT)/lib -lfesvr$(if $(PROFILE), -g -pg,) $(if $(DROMAJO), -L../corev_apu/tb/dromajo/src -ldromajo_cosim,) -lpthread" \
|
|
-CFLAGS "$(CFLAGS)$(if $(PROFILE), -g -pg,) $(if $(DROMAJO), -DDROMAJO=1,) -DVL_DEBUG" \
|
|
-Wall --cc --vpi \
|
|
$(list_incdir) --top-module ariane_testharness \
|
|
--threads-dpi none \
|
|
--Mdir $(ver-library) -O3 \
|
|
--exe corev_apu/tb/ariane_tb.cpp corev_apu/tb/dpi/SimDTM.cc corev_apu/tb/dpi/SimJTAG.cc \
|
|
corev_apu/tb/dpi/remote_bitbang.cc corev_apu/tb/dpi/msim_helper.cc $(if $(DROMAJO), corev_apu/tb/dpi/dromajo_cosim_dpi.cc,)
|
|
|
|
dromajo:
|
|
cd ./tb/dromajo/src && make
|
|
|
|
run-dromajo-verilator:
|
|
$(if $(BIN), $(MAKE) checkpoint_dromajo, $(error "Please provide absolute path to the binary. Usage: make run_dromajo BIN=/absolute/path/to/binary"))
|
|
|
|
checkpoint_dromajo:
|
|
cd ./tb/dromajo/run/checkpoints/ && \
|
|
rm -rf $(notdir $(BIN)) && mkdir $(notdir $(BIN)) && cd $(notdir $(BIN)) && \
|
|
cp $(BIN) . && \
|
|
echo -e "\
|
|
{\n\
|
|
\"version\":1,\n\
|
|
\"machine\":\"riscv64\",\n\
|
|
\"memory_size\":256,\n\
|
|
\"bios\":\"$(shell pwd)/tb/dromajo/run/checkpoints/$(notdir $(BIN))/$(notdir $(BIN))\",\n\
|
|
\"memory_base_addr\":0x80000000,\n\
|
|
\"missing_csrs\": [0x323, 0x324, 0x325, 0x326, //mhpmevent csrs\n\
|
|
0x327, 0x328, 0x329, 0x32a,\n\
|
|
0x32b, 0x32c, 0x32d, 0x32e,\n\
|
|
0x32f, 0x330, 0x331, 0x332,\n\
|
|
0x333, 0x334, 0x335, 0x336,\n\
|
|
0x337, 0x338, 0x339, 0x33a,\n\
|
|
0x33b, 0x33c, 0x33d, 0x33e,\n\
|
|
0x33f,\n\
|
|
0x3a0, 0x3a1, 0x3a2, 0x3a3, //pmp csrs\n\
|
|
0x3b0, 0x3b1, 0x3b2, 0x3b3,\n\
|
|
0x3b4, 0x3b5, 0x3b6, 0x3b7,\n\
|
|
0x3b8, 0x3b9, 0x3ba, 0x3bb,\n\
|
|
0x3bc, 0x3bd, 0x3be, 0x3bf,\n\
|
|
0x320], //mcountinhibit\n\
|
|
\"maxinsns\": 100,\n\
|
|
\"clint_base_addr\": 0x02000000,\n\
|
|
\"clint_size\": 0xC0000,\n\
|
|
\"plic_base_addr\": 0x0C000000,\n\
|
|
\"plic_size\": 0x3FFFFFF,\n\
|
|
\"uart_base_addr\": 0x10000000,\n\
|
|
\"uart_size\": 0x1000\n\
|
|
}" > "$(notdir $(BIN))_boot.cfg" && \
|
|
echo -e "\
|
|
{\n\
|
|
\"version\":1,\n\
|
|
\"machine\":\"riscv64\",\n\
|
|
\"memory_size\":256,\n\
|
|
\"bios\":\"$(shell pwd)/tb/dromajo/run/checkpoints/$(notdir $(BIN))/$(notdir $(BIN))\",\n\
|
|
\"load\":\"$(shell pwd)/tb/dromajo/run/checkpoints/$(notdir $(BIN))/$(notdir $(BIN))\",\n\
|
|
\"skip_commit\": [0x73, 0x9002, 0x100073],\n\
|
|
\"memory_base_addr\":0x80000000,\n\
|
|
\"clint_base_addr\": 0x02000000,\n\
|
|
\"clint_size\": 0xC0000,\n\
|
|
\"plic_base_addr\": 0x0C000000,\n\
|
|
\"plic_size\": 0x3FFFFFF,\n\
|
|
\"uart_base_addr\": 0x10000000,\n\
|
|
\"uart_size\": 0x1000\n\
|
|
}" > "$(notdir $(BIN)).cfg" && \
|
|
../../../src/dromajo --save=$(notdir $(BIN)) --save_format=1 ./$(notdir $(BIN))_boot.cfg && \
|
|
cd ../../../../../ && \
|
|
./work-ver/Variane_testharness +checkpoint=$(shell pwd)/tb/dromajo/run/checkpoints/$(notdir $(BIN))/$(notdir $(BIN))
|
|
|
|
|
|
# User Verilator, at some point in the future this will be auto-generated
|
|
verilate: $(if $(DROMAJO), dromajo,)
|
|
@echo "[Verilator] Building Model$(if $(PROFILE), for Profiling,)"
|
|
$(verilate_command)
|
|
cd $(ver-library) && $(MAKE) -j${NUM_JOBS} -f Variane_testharness.mk
|
|
|
|
sim-verilator: verilate
|
|
$(ver-library)/Variane_testharness $(elf-bin)
|
|
|
|
$(addsuffix -verilator,$(riscv-asm-tests)): verilate
|
|
$(ver-library)/Variane_testharness $(riscv-test-dir)/$(subst -verilator,,$@)
|
|
|
|
$(addsuffix -verilator,$(riscv-amo-tests)): verilate
|
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$(ver-library)/Variane_testharness $(riscv-test-dir)/$(subst -verilator,,$@)
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$(addsuffix -verilator,$(riscv-mul-tests)): verilate
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$(ver-library)/Variane_testharness $(riscv-test-dir)/$(subst -verilator,,$@)
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$(addsuffix -verilator,$(riscv-fp-tests)): verilate
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$(ver-library)/Variane_testharness $(riscv-test-dir)/$(subst -verilator,,$@)
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$(addsuffix -verilator,$(riscv-benchmarks)): verilate
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$(ver-library)/Variane_testharness $(riscv-benchmarks-dir)/$(subst -verilator,,$@)
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run-all-tests-verilator: $(addsuffix -verilator, $(riscv-asm-tests)) $(addsuffix -verilator, $(riscv-amo-tests)) $(addsuffix -verilator, $(run-mul-verilator)) $(addsuffix -verilator, $(riscv-fp-tests))
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run-asm-tests-verilator: $(addsuffix -verilator, $(riscv-asm-tests))
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run-amo-verilator: $(addsuffix -verilator, $(riscv-amo-tests))
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run-mul-verilator: $(addsuffix -verilator, $(riscv-mul-tests))
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run-fp-verilator: $(addsuffix -verilator, $(riscv-fp-tests))
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run-fp-d-verilator: $(addsuffix -verilator, $(filter rv64ud%, $(riscv-fp-tests)))
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run-fp-f-verilator: $(addsuffix -verilator, $(filter rv64uf%, $(riscv-fp-tests)))
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run-benchmarks-verilator: $(addsuffix -verilator,$(riscv-benchmarks))
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# torture-specific
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torture-gen:
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cd $(riscv-torture-dir) && $(riscv-torture-bin) 'generator/run'
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torture-itest:
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cd $(riscv-torture-dir) && $(riscv-torture-bin) 'testrun/run -a output/test.S'
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torture-rtest: build
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cd $(riscv-torture-dir) && printf "#!/bin/sh\ncd $(root-dir) && $(MAKE) run-torture$(torture-logs) batch-mode=1 defines=$(defines) test-location=$(test-location)" > call.sh && chmod +x call.sh
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cd $(riscv-torture-dir) && $(riscv-torture-bin) 'testrun/run -r ./call.sh -a $(test-location).S' | tee $(test-location).log
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make check-torture test-location=$(test-location)
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|
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torture-dummy: build
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cd $(riscv-torture-dir) && printf "#!/bin/sh\ncd $(root-dir) && $(MAKE) run-torture batch-mode=1 defines=$(defines) test-location=\$${@: -1}" > call.sh
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|
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torture-rnight: build
|
|
cd $(riscv-torture-dir) && printf "#!/bin/sh\ncd $(root-dir) && $(MAKE) run-torture$(torture-logs) batch-mode=1 defines=$(defines) test-location=\$${@: -1}" > call.sh && chmod +x call.sh
|
|
cd $(riscv-torture-dir) && $(riscv-torture-bin) 'overnight/run -r ./call.sh -g none' | tee output/overnight.log
|
|
$(MAKE) check-torture
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|
|
|
torture-rtest-verilator: verilate
|
|
cd $(riscv-torture-dir) && printf "#!/bin/sh\ncd $(root-dir) && $(MAKE) run-torture-verilator batch-mode=1 defines=$(defines)" > call.sh && chmod +x call.sh
|
|
cd $(riscv-torture-dir) && $(riscv-torture-bin) 'testrun/run -r ./call.sh -a output/test.S' | tee output/test.log
|
|
$(MAKE) check-torture
|
|
|
|
run-torture: build
|
|
$(VSIM) +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles)+UVM_TESTNAME=$(test_case) \
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|
+BASEDIR=$(riscv-torture-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(SPIKE_ROOT)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
|
|
${top_level}_optimized +permissive-off +signature=$(riscv-torture-dir)/$(test-location).rtlsim.sig ++$(riscv-torture-dir)/$(test-location) ++$(target-options)
|
|
|
|
run-torture-log: build
|
|
$(VSIM) +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles)+UVM_TESTNAME=$(test_case) \
|
|
+BASEDIR=$(riscv-torture-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(SPIKE_ROOT)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
|
|
${top_level}_optimized +permissive-off +signature=$(riscv-torture-dir)/$(test-location).rtlsim.sig ++$(riscv-torture-dir)/$(test-location) ++$(target-options)
|
|
cp vsim.wlf $(riscv-torture-dir)/$(test-location).wlf
|
|
cp trace_hart_0000.log $(riscv-torture-dir)/$(test-location).trace
|
|
cp trace_hart_0000_commit.log $(riscv-torture-dir)/$(test-location).commit
|
|
cp transcript $(riscv-torture-dir)/$(test-location).transcript
|
|
|
|
run-torture-verilator: verilate
|
|
$(ver-library)/Variane_testharness +max-cycles=$(max_cycles) +signature=$(riscv-torture-dir)/output/test.rtlsim.sig $(riscv-torture-dir)/output/test
|
|
|
|
check-torture:
|
|
grep 'All signatures match for $(test-location)' $(riscv-torture-dir)/$(test-location).log
|
|
diff -s $(riscv-torture-dir)/$(test-location).spike.sig $(riscv-torture-dir)/$(test-location).rtlsim.sig
|
|
|
|
fpga_filter := $(addprefix $(root-dir), corev_apu/bootrom/bootrom.sv)
|
|
fpga_filter += $(addprefix $(root-dir), core/include/instr_tracer_pkg.sv)
|
|
fpga_filter += $(addprefix $(root-dir), src/util/ex_trace_item.sv)
|
|
fpga_filter += $(addprefix $(root-dir), src/util/instr_trace_item.sv)
|
|
fpga_filter += $(addprefix $(root-dir), common/local/util/instr_tracer_if.sv)
|
|
fpga_filter += $(addprefix $(root-dir), common/local/util/instr_tracer.sv)
|
|
|
|
fpga: $(ariane_pkg) $(util) $(src) $(fpga_src) $(uart_src) $(copro_src)
|
|
@echo "[FPGA] Generate sources"
|
|
@echo read_vhdl {$(uart_src)} > corev_apu/fpga/scripts/add_sources.tcl
|
|
@echo read_verilog -sv {$(ariane_pkg)} >> corev_apu/fpga/scripts/add_sources.tcl
|
|
@echo read_verilog -sv {$(filter-out $(fpga_filter), $(util))} >> corev_apu/fpga/scripts/add_sources.tcl
|
|
@echo read_verilog -sv {$(filter-out $(fpga_filter), $(copro_src))} >> corev_apu/fpga/scripts/add_sources.tcl
|
|
@echo read_verilog -sv {$(filter-out $(fpga_filter), $(src))} >> corev_apu/fpga/scripts/add_sources.tcl
|
|
@echo read_verilog -sv {$(fpga_src)} >> corev_apu/fpga/scripts/add_sources.tcl
|
|
@echo "[FPGA] Generate Bitstream"
|
|
cd corev_apu/fpga && make BOARD=$(BOARD) XILINX_PART=$(XILINX_PART) XILINX_BOARD=$(XILINX_BOARD) CLK_PERIOD_NS=$(CLK_PERIOD_NS)
|
|
|
|
.PHONY: fpga
|
|
|
|
build-spike:
|
|
cd tb/riscv-isa-sim && mkdir -p build && cd build && ../configure --prefix=`pwd`/../install --with-fesvr=$(RISCV) --enable-commitlog && make -j8 install
|
|
|
|
clean:
|
|
rm -rf $(riscv-torture-dir)/output/test*
|
|
rm -rf $(library)/ $(dpi-library)/ $(ver-library)/ $(vcs-library)/
|
|
rm -f tmp/*.ucdb tmp/*.log *.wlf *vstf wlft* *.ucdb
|
|
cd corev_apu/fpga && make clean && cd ../..
|
|
|
|
.PHONY:
|
|
build sim sim-verilate clean \
|
|
$(riscv-asm-tests) $(addsuffix _verilator,$(riscv-asm-tests)) \
|
|
$(riscv-benchmarks) $(addsuffix _verilator,$(riscv-benchmarks)) \
|
|
check-benchmarks check-asm-tests \
|
|
torture-gen torture-itest torture-rtest \
|
|
run-torture run-torture-verilator check-torture check-torture-verilator
|