mirror of
https://github.com/openhwgroup/cva6.git
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574 lines
16 KiB
Python
574 lines
16 KiB
Python
# Copyright 2024 Thales Silicon Security
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#
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# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
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# You may obtain a copy of the License at https://solderpad.org/licenses/
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#
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# Original Author: Côme ALLART - Thales
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"""
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Represents the instruction set
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"""
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from dataclasses import dataclass
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class Reg:
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"""Constants to represent registers"""
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# ABI names
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zero = 0
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ra = 1
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sp = 2
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gp = 3
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tp = 4
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t0 = 5
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t1 = 6
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t2 = 7
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s0 = 8
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fp = 8
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s1 = 9
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a0 = 10
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a1 = 11
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a2 = 12
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a3 = 13
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a4 = 14
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a5 = 15
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a6 = 16
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a7 = 17
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s2 = 18
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s3 = 19
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s4 = 20
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s5 = 21
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s6 = 22
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s7 = 23
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s8 = 24
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s9 = 25
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s10 = 26
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s11 = 27
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t3 = 28
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t4 = 29
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t5 = 30
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t6 = 31
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# Register names
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x0 = 0
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x1 = 1
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x2 = 2
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x3 = 3
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x4 = 4
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x5 = 5
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x6 = 6
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x7 = 7
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x8 = 8
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x9 = 9
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x10 = 10
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x11 = 11
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x12 = 12
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x13 = 13
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x14 = 14
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x15 = 15
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x16 = 16
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x17 = 17
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x18 = 18
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x19 = 19
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x20 = 20
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x21 = 21
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x22 = 22
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x23 = 23
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x24 = 24
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x25 = 25
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x26 = 26
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x27 = 27
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x28 = 28
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x29 = 29
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x30 = 30
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x31 = 31
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def sign_ext(imm, index, xlen=32):
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"""
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Sign extends a value
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imm: value to sign extend
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index: index of the sign bit of the value
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len: target len for sign extended value
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"""
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imm_bits = index + 1
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assert (imm >> imm_bits) == 0
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neg = imm >> index
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sext_bits = xlen - imm_bits
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sext_ones = (1 << sext_bits) - 1
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sext = neg * sext_ones << imm_bits
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return sext | imm
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@dataclass
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class AddrFields:
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"""Represents the data used to build a memory address"""
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base_reg: int
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offset: int
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class Rtype:
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"""R-type instructions"""
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def __init__(self, instr):
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self.funct7 = instr.bin >> 25
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self.rs2 = (instr.bin >> 20) & 31
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self.rs1 = (instr.bin >> 15) & 31
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self.funct3 = (instr.bin >> 12) & 7
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self.rd = (instr.bin >> 7) & 31
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self.opcode = instr.bin & 63
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class Itype:
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"""I-type instructions"""
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def __init__(self, instr):
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self.rs1 = (instr.bin >> 15) & 31
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self.funct3 = (instr.bin >> 12) & 7
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self.rd = (instr.bin >> 7) & 31
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self.opcode = instr.bin & 63
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self.imm = sign_ext(instr.bin >> 20, 11)
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class Stype:
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"""S-type instructions"""
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def __init__(self, instr):
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self.rs2 = (instr.bin >> 20) & 31
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self.rs1 = (instr.bin >> 15) & 31
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self.funct3 = (instr.bin >> 12) & 7
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self.opcode = instr.bin & 63
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self.imm = sign_ext(
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((instr.bin >> 25) << 5) \
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| ((instr.bin >> 7) & 31)
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, 11)
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class Btype:
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"""B-type instructions"""
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def __init__(self, instr):
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self.rs2 = (instr.bin >> 20) & 31
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self.rs1 = (instr.bin >> 15) & 31
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self.funct3 = (instr.bin >> 12) & 7
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self.opcode = instr.bin & 63
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self.imm = sign_ext(
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((instr.bin >> 31) << 12) \
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| (((instr.bin >> 7) & 1) << 11) \
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| (((instr.bin >> 25) & 0x3f) << 5) \
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| (((instr.bin >> 8) & 15) << 1)
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, 12)
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class Utype:
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"""U-type instructions"""
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def __init__(self, instr):
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self.imm_31_12 = instr.bin >> 12
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self.imm_4_0 = (instr.bin >> 7) & 31
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self.rd = (instr.bin >> 7) & 31
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self.opcode = instr.bin & 63
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self.imm = self.imm_31_12 << 12
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class Jtype:
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"""J-type instructions"""
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def __init__(self, instr):
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self.rd = (instr.bin >> 7) & 31
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self.opcode = instr.bin & 63
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self.imm = sign_ext(
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((instr.bin >> 31) << 20) \
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| (((instr.bin >> 12) & 0xff) << 12) \
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| (((instr.bin >> 20) & 1) << 11) \
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| (((instr.bin >> 21) & 0x3ff) << 1)
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, 20)
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class MOItype:
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"""Memory ordering instructions"""
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def __init__(self, instr):
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self.fm = instr.bin >> 28
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self.PI = (instr.bin >> 27) & 1
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self.PO = (instr.bin >> 26) & 1
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self.PR = (instr.bin >> 25) & 1
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self.PW = (instr.bin >> 24) & 1
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self.SI = (instr.bin >> 23) & 1
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self.SO = (instr.bin >> 22) & 1
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self.SR = (instr.bin >> 21) & 1
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self.SW = (instr.bin >> 20) & 1
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self.rs1 = (instr.bin >> 15) & 31
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self.funct3 = (instr.bin >> 12) & 7
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self.rd = (instr.bin >> 7) & 31
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self.opcode = instr.bin & 63
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class CRtype:
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"""Compressed register"""
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def __init__(self, instr):
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self.funct4 = instr.bin >> 12
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r = (instr.bin >> 7) & 31
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self.rs2 = (instr.bin >> 2) & 31
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self.op = instr.bin & 3
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self.rs1 = r
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base = instr.base()
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if base == 'C.J[AL]R/C.MV/C.ADD':
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if self.funct4 & 1:
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if self.rs2 == 0:
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if r == 0:
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base = 'C.EBREAK'
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else:
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base = 'C.JALR'
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else:
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base = 'C.ADD'
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else:
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if self.rs2 == 0:
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base = 'C.JR'
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else:
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base = 'C.MV'
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if base in CRtype.regreg:
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self.rd = r
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self.name = base
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control = ['C.JR', 'C.JALR']
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regreg = ['C.MV', 'C.ADD']
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class CItype:
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"""Compressed immediate"""
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def __init__(self, instr):
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self.funct3 = instr.bin >> 13
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r = (instr.bin >> 7) & 31
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self.op = instr.bin & 3
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base = instr.base()
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if base == 'C.LUI/C.ADDI16SP':
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if r == Reg.sp:
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base = 'C.ADDI16SP'
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else:
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base = 'C.LUI'
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if base in CItype.SPload + CItype.constgen:
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self.rd = r
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if base in CItype.SPload:
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self.rs1 = Reg.sp
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self.offset = CItype.offset[base](instr.bin)
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# zero-extended offset
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if base == 'C.LI':
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self.imm = sign_ext(CItype.imm(instr.bin), 5)
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if base == 'C.LUI':
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self.nzimm = sign_ext(CItype.imm(instr.bin) << 12, 17)
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if base in CItype.regimm:
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self.rd = r
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self.rs1 = r
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if base == 'C.ADDI':
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self.nzimm = sign_ext(CItype.imm(instr.bin), 5)
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if base == 'C.ADDIW':
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self.imm = sign_ext(CItype.imm(instr.bin), 5)
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if base == 'C.ADDI16SP':
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self.nzimm = sign_ext(CItype.immsp(instr.bin), 9)
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if base == 'C.SLLI':
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self.shamt = CItype.imm(instr.bin)
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SPload = ['C.LWSP', 'C.LDSP', 'C.LQSP', 'C.FLWSP', 'C.FLDSP']
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constgen = ['C.LI', 'C.LUI']
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regimm = ['C.ADDI', 'C.ADDIW', 'C.ADDI16SP', 'C.SLLI']
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Woffset = lambda i: (((i >> 12) & 1) << 5) | (((i >> 4) & 7) << 2) \
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| (((i >> 2) & 3) << 6)
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Doffset = lambda i: (((i >> 12) & 1) << 5) | (((i >> 5) & 3) << 3) \
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| (((i >> 2) & 7) << 6)
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Qoffset = lambda i: (((i >> 12) & 1) << 5) | (((i >> 6) & 1) << 4) \
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| (((i >> 2) & 15) << 6)
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imm = lambda i: (((i >> 12) & 1) << 5) | ((i >> 2) & 31)
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immsp = lambda i: (((i >> 12) & 1) << 9) | (((i >> 6) & 1) << 4) \
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| (((i >> 5) & 1) << 6) | (((i >> 3) & 3) << 7) \
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| (((i >> 2) & 1) << 5)
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offset = {
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'C.LWSP': Woffset,
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'C.LDSP': Doffset,
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'C.LQSP': Qoffset,
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'C.FLWSP': Woffset,
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'C.FLDSP': Doffset,
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}
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class CSStype:
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"""Compressed stack-relative store"""
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def __init__(self, instr):
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self.funct3 = instr.bin >> 13
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self.rs1 = Reg.sp
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self.rs2 = (instr.bin >> 2) & 31
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self.op = instr.bin & 3
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self.offset = CSStype.offset[instr.base()](instr.bin)
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# zero-extended offset
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Woffset = lambda i: (((i >> 9) & 15) << 2) | (((i >> 7) & 3) << 6)
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Doffset = lambda i: (((i >> 10) & 7) << 3) | (((i >> 7) & 7) << 6)
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Qoffset = lambda i: (((i >> 11) & 3) << 4) | (((i >> 7) & 15) << 6)
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offset = {
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'C.SWSP': Woffset,
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'C.SDSP': Doffset,
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'C.SQSP': Qoffset,
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'C.FSWSP': Woffset,
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'C.FSDSP': Doffset,
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}
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class CIWtype:
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"""Compressed wide immediate"""
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def __init__(self, instr):
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i = instr.bin
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self.funct3 = i >> 13
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rd_ = (i >> 2) & 7
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self.rd = rd_ + 8
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self.op = i & 3
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self.nzuimm = (((i >> 11) & 3) << 4) | (((i >> 7) & 15) << 6) \
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| (((i >> 6) & 1) << 2) | (((i >> 5) & 1) << 3)
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# zero-extended (unsigned) non-zero immediate
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if instr.base() == 'C.ADDI4SPN':
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self.rs1 = Reg.sp
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CLS_Woffset = lambda i: (((i >> 10) & 7) << 3) | (((i >> 6) & 1) << 2) \
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| (((i >> 5) & 1) << 6)
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CLS_Doffset = lambda i: (((i >> 10) & 7) << 3) | (((i >> 5) & 3) << 6)
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CLS_Qoffset = lambda i: (((i >> 11) & 3) << 4) | (((i >> 10) & 1) << 8) \
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| (((i >> 5) & 3) << 6)
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class CLtype:
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"""Compressed load"""
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def __init__(self, instr):
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self.funct3 = instr.bin >> 13
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rs1_ = (instr.bin >> 7) & 7
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rd_ = (instr.bin >> 2) & 7
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self.rs1 = rs1_ + 8
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self.rd = rd_ + 8
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self.op = instr.bin & 3
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self.offset = CLtype.offset[instr.base()](instr.bin)
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# zero-extended offset
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offset = {
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'C.LW': CLS_Woffset,
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'C.LD': CLS_Doffset,
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'C.LQ': CLS_Qoffset,
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'C.FLW': CLS_Woffset,
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'C.FLD': CLS_Doffset,
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}
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class CStype:
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"""Compressed store"""
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def __init__(self, instr):
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self.funct3 = instr.bin >> 13
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rs1_ = (instr.bin >> 7) & 7
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rs2_ = (instr.bin >> 2) & 7
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self.rs1 = rs1_ + 8
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self.rs2 = rs2_ + 8
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self.op = instr.bin & 3
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self.offset = CStype.offset[instr.base()](instr.bin)
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# zero-extended offset
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offset = {
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'C.SW': CLS_Woffset,
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'C.SD': CLS_Doffset,
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'C.SQ': CLS_Qoffset,
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'C.FSW': CLS_Woffset,
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'C.FSD': CLS_Doffset,
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}
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class CAtype:
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"""Compressed arithmetic"""
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def __init__(self, instr):
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self.funct6 = instr.bin >> 10
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r = (instr.bin >> 7) & 7
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self.rd = r + 8
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self.rs1 = r + 8
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self.funct2 = (instr.bin >> 5) & 3
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self.rs2 = ((instr.bin >> 2) & 7) + 8
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self.op = instr.bin & 3
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class CBtype:
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"""Compressed branch"""
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def __init__(self, instr):
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i = instr.bin
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base = instr.base()
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self.funct3 = i >> 13
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self.offset = (i >> 10) & 7
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rs1_ = (i >> 7) & 7
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self.rs1 = rs1_ + 8
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self.op = instr.bin & 3
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if base in CBtype.branch:
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self.offset = sign_ext(
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(((i >> 12) & 1) << 8) \
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| (((i >> 10) & 3) << 3) \
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| (((i >> 5) & 3) << 6) \
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| (((i >> 3) & 3) << 1) \
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| (((i >> 2) & 1) << 5)
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, 8)
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if base in CBtype.regimm:
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if base == 'C.ANDI':
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self.shamt = sign_ext(CItype.imm(i), 5)
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else:
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self.shamt = CItype.imm(i)
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self.rd = self.rs1
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branch = ['C.BEQZ', 'C.BNEZ']
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regimm = ['C.SRLI', 'C.SRAI', 'C.ANDI']
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class CJtype:
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"""Compressed jump"""
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def __init__(self, instr):
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self.funct3 = instr.bin >> 13
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assert instr.base() in ['C.J', 'C.JAL']
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self.offset = sign_ext(CJtype.offset(instr.bin), 11)
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self.jump_target = (instr.bin >> 2) & 0x7ff
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self.op = instr.bin & 3
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offset = lambda i: (((i >> 12) & 1) << 11) | (((i << 11) & 1) << 4) \
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| (((i >> 9) & 3) << 8) | (((i >> 8) & 1) << 10) \
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| (((i >> 7) & 1) << 6) | (((i >> 6) & 1) << 7) \
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| (((i >> 3) & 1) << 1) | (((i >> 2) & 1) << 5)
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class Instr:
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"""Instructions"""
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table_16_4_RV32 = [
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['C.ADDI4SPN', 'C.FLD', 'C.LW', 'C.FLW',
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'Reserved', 'C.FSD', 'C.SW', 'C.FSW'],
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['C.ADDI', 'C.JAL', 'C.LI', 'C.LUI/C.ADDI16SP',
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'MISC-ALU', 'C.J', 'C.BEQZ', 'C.BNEZ'],
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['C.SLLI', 'C.FLDSP', 'C.LWSP', 'C.FLWSP',
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'C.J[AL]R/C.MV/C.ADD', 'C.FSDSP', 'C.SWSP', 'C.FSWSP'],
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]
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table_24_1 = [
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['LOAD', 'LOAD-FP', 'custom-0', 'MISC-MEM', 'OP-IMM', 'AUIPC', 'OP-IMM-32', '48b'],
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['STORE', 'STORE-FP', 'custom-1', 'AMO', 'OP', 'LUI', 'OP-32', '64b'],
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['MADD', 'MSUB', 'NMSUB', 'NMADD', 'OP-FP', 'reserved', 'custom-2/rv128', '48b'],
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['BRANCH', 'JALR', 'reserved', 'JAL', 'SYSTEM', 'reserved', 'custom-3/rv128', '80b'],
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]
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type_of_base = {
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'OP-IMM': Itype,
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'LUI': Utype,
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'AUIPC': Utype,
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'OP': Rtype,
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'OP-32': Rtype,
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'JAL': Jtype,
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'JALR': Itype,
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'BRANCH': Btype,
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'LOAD': Itype,
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'STORE': Stype,
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'SYSTEM': Itype,
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'C.LWSP': CItype,
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'C.LDSP': CItype,
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'C.LQSP': CItype,
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'C.FLWSP': CItype,
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'C.FLDSP': CItype,
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'C.SWSP': CSStype,
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'C.SDSP': CSStype,
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'C.SQSP': CSStype,
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'C.FSWSP': CSStype,
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'C.FSDSP': CSStype,
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'C.LW': CLtype,
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'C.LD': CLtype,
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'C.LQ': CLtype,
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'C.FLW': CLtype,
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'C.FLD': CLtype,
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'C.SW': CStype,
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'C.SD': CStype,
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'C.SQ': CStype,
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'C.FSW': CStype,
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'C.FSD': CStype,
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'C.J': CJtype,
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'C.JAL': CJtype,
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'C.J[AL]R/C.MV/C.ADD': CRtype,
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'C.BEQZ': CBtype,
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'C.BNEZ': CBtype,
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'C.LI': CItype,
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'C.LUI/C.ADDI16SP': CItype,
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'C.ADDI': CItype,
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'C.ADDIW': CItype,
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'C.ADDI4SPN': CIWtype,
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'C.SLLI': CItype,
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'MISC-ALU': CAtype,
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}
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iloads = ['C.LW', 'C.LWSP', 'LOAD']
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floads = ['C.FLD', 'C.FLW', 'C.FLDSP', 'C.FLWSP', 'LOAD-FP']
|
|
istores = ['C.SW', 'C.SWSP', 'STORE']
|
|
fstores = ['C.FSD', 'C.FSW', 'C.FSDSP', 'C.FSWSP', 'STORE-FP']
|
|
loads = iloads + floads
|
|
stores = istores + fstores
|
|
|
|
def __init__(self, bincode):
|
|
self.bin = bincode
|
|
self.inst_1_0 = self.bin & 3
|
|
|
|
def base(self):
|
|
"""Get the name of the base instruction"""
|
|
result = ""
|
|
if self.is_compressed():
|
|
line = self.bin & 3
|
|
col = (self.bin >> 13) & 7
|
|
result = Instr.table_16_4_RV32[line][col]
|
|
else:
|
|
line = (self.bin >> 5) & 3
|
|
col = (self.bin >> 2) & 7
|
|
result = Instr.table_24_1[line][col]
|
|
return result
|
|
|
|
def fields(self):
|
|
"""Get an object with the fields of the instruction"""
|
|
return Instr.type_of_base[self.base()](self)
|
|
|
|
def is_compressed(self):
|
|
"""Is the instruction from the C extension?"""
|
|
return (self.bin & 3) < 3
|
|
|
|
def size(self):
|
|
"""Size of the instruction in bytes"""
|
|
return 2 if self.is_compressed() else 4
|
|
|
|
def is_load(self):
|
|
"""Is the instruction a load?"""
|
|
return self.base() in Instr.loads
|
|
|
|
def is_store(self):
|
|
"""Is the instruction a store?"""
|
|
return self.base() in Instr.stores
|
|
|
|
def is_branch(self):
|
|
"""Is it a taken/not taken branch?"""
|
|
return self.base() in ['C.BEQZ', 'C.BNEZ', 'BRANCH']
|
|
|
|
def is_regjump(self):
|
|
"""Is it a register jump?"""
|
|
if self.base() in ['JALR']:
|
|
return True
|
|
if self.base() == 'C.J[AL]R/C.MV/C.ADD':
|
|
return self.fields().name in ['C.JALR', 'C.JR']
|
|
return False
|
|
|
|
def is_jump(self):
|
|
"""Is it an immediate jump?"""
|
|
return self.base() in ['JAL', 'C.JAL', 'C.J']
|
|
|
|
def is_muldiv(self):
|
|
"""Is it a muldiv instruction?"""
|
|
return self.base() in ['OP', 'OP-32'] and self.fields().funct7 == 1
|
|
|
|
def offset(self):
|
|
"""Get offset from instr (sometimes it is just 'imm' in RISCV spec)"""
|
|
fields = self.fields()
|
|
return fields.offset if hasattr(fields, 'offset') else fields.imm
|
|
|
|
def addr_fields(self):
|
|
"""Get the register and offset to build an address"""
|
|
return AddrFields(self.fields().rs1, self.offset())
|
|
|
|
def has_WAW_from(self, other):
|
|
"""b.has_WAW_from(a) if a.rd == b.rd"""
|
|
a = other.fields()
|
|
b = self.fields()
|
|
if not (hasattr(a, 'rd') and hasattr(b, 'rd')):
|
|
return False
|
|
return a.rd == b.rd and a.rd != Reg.zero
|
|
|
|
def has_RAW_from(self, other):
|
|
"""b.has_RAW_from(a) if b.rsX == a.rd"""
|
|
a = other.fields()
|
|
b = self.fields()
|
|
if not hasattr(a, 'rd') or a.rd == Reg.zero:
|
|
return False
|
|
if hasattr(b, 'rs1') and a.rd == b.rs1:
|
|
return True
|
|
return hasattr(b, 'rs2') and a.rd == b.rs2
|
|
|
|
def has_WAR_from(self, other):
|
|
"""b.has_WAR_from(a) if b.rd == a.rsX"""
|
|
a = other.fields()
|
|
b = self.fields()
|
|
if not hasattr(b, 'rd') or b.rd == Reg.zero:
|
|
return False
|
|
if hasattr(a, 'rs1') and a.rs1 == b.rd:
|
|
return True
|
|
return hasattr(a, 'rs2') and a.rs2 == b.rd
|