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666 lines
21 KiB
Python
666 lines
21 KiB
Python
# Copyright 2024 Thales Silicon Security
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#
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# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
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# You may obtain a copy of the License at https://solderpad.org/licenses/
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#
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# Original Author: Côme ALLART - Thales
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"""
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Performance model of the cva6
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"""
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import sys
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import re
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from dataclasses import dataclass
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from enum import Enum
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from collections import defaultdict
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#from matplotlib import pyplot as plt
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from isa import Instr, Reg
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EventKind = Enum('EventKind', [
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'WAW', 'WAR', 'RAW',
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'BMISS', 'BHIT',
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'STRUCT',
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'issue', 'done', 'commit',
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])
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def to_signed(value, xlen=32):
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signed = value
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if signed >> (xlen - 1):
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signed -= 1 << xlen
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return signed
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class Event:
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"""Represents an event on an instruction"""
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def __init__(self, kind, cycle):
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self.kind = kind
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self.cycle = cycle
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def __repr__(self):
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return f"@{self.cycle}: {self.kind}"
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class Instruction(Instr):
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"""Represents a RISC-V instruction with annotations"""
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def __init__(self, line, address, hex_code, mnemo):
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Instr.__init__(self, int(hex_code, base=16))
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self.line = line
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self.address = int(address, base=16)
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self.hex_code = hex_code
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self.mnemo = mnemo
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self.events = []
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def mnemo_name(self):
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"""The name of the instruction (fisrt word of the mnemo)"""
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return self.mnemo.split()[0]
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def next_addr(self):
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"""Address of next instruction"""
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return self.address + self.size()
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_ret_regs = [Reg.ra, Reg.t0]
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def is_ret(self):
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"Does CVA6 consider this instruction as a ret?"
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f = self.fields()
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# Strange conditions, no imm check, no rd-discard check
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return self.is_regjump() \
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and f.rs1 in Instruction._ret_regs \
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and (self.is_compressed() or f.rs1 != f.rd)
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def is_call(self):
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"Does CVA6 consider this instruction as a ret?"
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base = self.base()
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f = self.fields()
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return base == 'C.JAL' \
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or base == 'C.J[AL]R/C.MV/C.ADD' and f.name == 'C.JALR' \
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or base in ['JAL', 'JALR'] and f.rd in Instruction._ret_regs
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def __repr__(self):
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return self.mnemo
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@dataclass
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class Entry:
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"""A scoreboard entry"""
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instr: Instruction
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cycles_since_issue = 0
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done: bool = False
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def __repr__(self):
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status = "DONE" if self.done else "WIP "
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addr = f"0x{self.instr.address:08X}"
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return f"{status} {addr}:`{self.instr}` for {self.cycles_since_issue}"
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@dataclass
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class LastIssue:
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"""To store the last issued instruction"""
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instr: Instruction
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issue_cycle: int
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class IqLen:
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"""Model of the instruction queue with only a size counter"""
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def __init__(self, fetch_size, debug=False):
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self.fetch_size = 4
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while self.fetch_size < fetch_size:
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self.fetch_size <<= 1
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self.debug = debug
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self.len = self.fetch_size
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self.new_fetch = True
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def fetch(self):
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"""Fetch bytes"""
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self.len += self.fetch_size
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self._debug(f"fetched {self.fetch_size}, got {self.len}")
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self.new_fetch = True
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def flush(self):
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"""Flush instruction queue (bmiss or exception)"""
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self.len = 0
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self._debug(f"flushed, got {self.len}")
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self.new_fetch = False
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def jump(self):
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"""Loose a fetch cycle and truncate (jump, branch hit taken)"""
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if self.new_fetch:
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self.len -= self.fetch_size
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self._debug(f"jumping, removed {self.fetch_size}, got {self.len}")
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self.new_fetch = False
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self._truncate()
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self._debug(f"jumped, got {self.len}")
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def has(self, instr):
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"""Does the instruction queue have this instruction?"""
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length = self.len
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if self._is_crossword(instr):
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length -= (self.fetch_size - 2)
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self._debug(f"comparing {length} to {instr.size()} ({instr})")
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return length >= instr.size()
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def remove(self, instr):
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"""Remove instruction from queue"""
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self.len -= instr.size()
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self._debug(f"removed {instr.size()}, got {self.len}")
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self._truncate(self._addr_index(instr.next_addr()))
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if instr.is_jump():
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self.jump()
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def _addr_index(self, addr):
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return addr & (self.fetch_size - 1)
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def _is_crossword(self, instr):
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is_last = self._addr_index(instr.address) == self.fetch_size - 2
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return is_last and not instr.is_compressed()
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def _truncate(self, index=0):
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occupancy = self.fetch_size - self._addr_index(self.len)
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to_remove = index - occupancy
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if to_remove < 0:
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to_remove += self.fetch_size
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self.len -= to_remove
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self._debug(f"truncated, removed {to_remove}, got {self.len}")
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def _debug(self, message):
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if self.debug:
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print(f"iq: {message}")
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class Ras:
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"Return Address Stack"
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def __init__(self, depth=2, debug=False):
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self.depth = depth - 1
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self.stack = []
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self.debug = debug
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self.last_dropped = None
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def push(self, addr):
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"Push an address on the stack, forget oldest entry if full"
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self.stack.append(addr)
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self._debug(f"pushed 0x{addr:08X}")
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if len(self.stack) > self.depth:
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self.stack.pop(0)
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self._debug("overflown")
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def drop(self):
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"Drop an address from the stack"
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self._debug("dropping")
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if len(self.stack) > 0:
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self.last_dropped = self.stack.pop()
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else:
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self.last_dropped = None
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self._debug("was already empty")
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def read(self):
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"Read the top of the stack without modifying it"
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self._debug("reading")
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if self.last_dropped is not None:
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addr = self.last_dropped
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self._debug(f"read 0x{addr:08X}")
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return addr
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self._debug("was empty")
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return None
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def resolve(self, instr):
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"Push or pop depending on the instruction"
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self._debug(f"issuing {instr}")
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if instr.is_ret():
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self._debug("detected ret")
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self.drop()
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if instr.is_call():
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self._debug("detected call")
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self.push(instr.next_addr())
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def _debug(self, message):
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if self.debug:
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print(f"RAS: {message}")
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class Bht:
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"Branch History Table"
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@dataclass
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class Entry:
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"A BTB entry"
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valid: bool = False
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sat_counter: int = 0
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def __init__(self, entries=128):
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self.contents = [Bht.Entry() for _ in range(entries)]
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def predict(self, addr):
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"Is the branch taken? None if don't know"
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entry = self.contents[self._index(addr)]
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if entry.valid:
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return entry.sat_counter >= 2
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return None
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def resolve(self, addr, taken):
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"Update branch prediction"
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index = self._index(addr)
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entry = self.contents[index]
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entry.valid = True
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if taken:
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if entry.sat_counter < 3:
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entry.sat_counter += 1
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else:
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if entry.sat_counter > 0:
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entry.sat_counter -= 1
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def _index(self, addr):
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return (addr >> 1) % len(self.contents)
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Fu = Enum('Fu', ['ALU', 'MUL', 'BRANCH', 'LDU', 'STU'])
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# We have
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# - FLU gathering ALU + BRANCH (+ CSR, not significant in CoreMark)
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# - LSU for loads and stores
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# - FP gathering MUL + second ALU (+ Floating, unused in CoreMark)
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# This way we do not have more write-back ports than currently with F
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def to_fu(instr):
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if instr.is_branch() or instr.is_regjump():
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return Fu.BRANCH
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if instr.is_muldiv():
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return Fu.MUL
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if instr.is_load():
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return Fu.LDU
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if instr.is_store():
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return Fu.STU
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return Fu.ALU
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class FusBusy:
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"Is each functional unit busy"
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def __init__(self, has_alu2 = False):
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self.has_alu2 = has_alu2
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self.alu = False
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self.mul = False
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self.branch = False
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self.ldu = False
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self.stu = False
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self.alu2 = False
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self.issued_mul = False
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def _alu2_ready(self):
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return self.has_alu2 and not self.alu2
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def is_ready(self, fu):
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return {
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Fu.ALU: self._alu2_ready() or not self.alu,
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Fu.MUL: not self.mul,
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Fu.BRANCH: not self.branch,
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Fu.LDU: not self.ldu,
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Fu.STU: not self.stu,
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}[fu]
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def is_ready_for(self, instr):
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return self.is_ready(to_fu(instr))
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def issue(self, instr):
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return {
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Fu.ALU: FusBusy.issue_alu,
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Fu.MUL: FusBusy.issue_mul,
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Fu.BRANCH: FusBusy.issue_branch,
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Fu.LDU: FusBusy.issue_ldu,
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Fu.STU: FusBusy.issue_stu,
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}[to_fu(instr)](self)
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def issue_mul(self):
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self.mul = True
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self.issued_mul = True
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def issue_alu(self):
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if not self._alu2_ready():
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assert not self.alu
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self.alu = True
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self.branch = True
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else:
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self.alu2 = True
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def issue_branch(self):
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self.alu = True
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self.branch = True
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# Stores are not allowed yet
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self.stu = True
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def issue_ldu(self):
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self.ldu = True
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self.stu = True
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def issue_stu(self):
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self.stu = True
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self.ldu = True
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def cycle(self):
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self.alu = self.issued_mul
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self.mul = False
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self.branch = self.issued_mul
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self.ldu = False
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self.stu = False
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self.alu2 = False
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self.issued_mul = False
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class Model:
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"""Models the scheduling of CVA6"""
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re_instr = re.compile(
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r"([a-z]+)\s+0:\s*0x00000000([0-9a-f]+)\s*\(([0-9a-fx]+)\)\s*@\s*([0-9]+)\s*(.*)"
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)
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def __init__(
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self,
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debug=False,
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issue=1,
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commit=2,
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sb_len=8,
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fetch_size=None,
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has_forwarding=True,
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has_renaming=True):
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self.ras = Ras(debug=debug)
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self.bht = Bht()
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self.instr_queue = []
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self.scoreboard = []
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self.fus = FusBusy(issue > 1)
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self.last_issued = None
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self.last_committed = None
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self.retired = []
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self.sb_len = sb_len
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self.debug = debug
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self.iqlen = IqLen(fetch_size or 4 * issue, debug)
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self.issue_width = issue
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self.commit_width = commit
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self.has_forwarding = has_forwarding
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self.has_renaming = has_renaming
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self.log = []
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def log_event_on(self, instr, kind, cycle):
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"""Log an event on the instruction"""
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if self.debug:
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print(f"{instr}: {kind}")
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event = Event(kind, cycle)
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instr.events.append(event)
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self.log.append((event, instr))
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def predict_branch(self, instr):
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"""Predict if branch is taken or not"""
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pred = self.bht.predict(instr.address)
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if pred is not None:
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return pred
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return instr.offset() >> 31 != 0
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def predict_regjump(self, instr):
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"""Predict destination address of indirect jump"""
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if instr.is_ret():
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return self.ras.read() or 0
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return 0 # always miss, as there is no btb yet
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def predict_pc(self, last):
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"""Predict next program counter depending on last issued instruction"""
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if last.is_branch():
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taken = self.predict_branch(last)
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offset = to_signed(last.offset()) if taken else last.size()
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return last.address + offset
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if last.is_regjump():
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return self.predict_regjump(last)
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return None
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def issue_manage_last_branch(self, instr, cycle):
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"""Flush IQ if branch miss, jump if branch hit"""
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if self.last_issued is not None:
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last = self.last_issued.instr
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pred = self.predict_pc(last)
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if pred is not None:
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bmiss = pred != instr.address
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resolved = cycle >= self.last_issued.issue_cycle + 6
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if bmiss and not resolved:
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self.iqlen.flush()
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branch = EventKind.BMISS if bmiss else EventKind.BHIT
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if branch not in [e.kind for e in instr.events]:
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self.log_event_on(instr, branch, cycle)
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taken = instr.address != last.next_addr()
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if taken and not bmiss:
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# last (not instr) was like a jump
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self.iqlen.jump()
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def commit_manage_last_branch(self, instr, cycle):
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"Resolve branch prediction"
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if self.last_committed is not None:
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last = self.last_committed
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if last.is_branch():
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taken = instr.address != last.next_addr()
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self.bht.resolve(last.address, taken)
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self.last_committed = instr
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def find_data_hazards(self, instr, cycle):
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"""Detect and log data hazards"""
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found = False
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for entry in self.scoreboard:
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if instr.has_WAW_from(entry.instr) and not self.has_renaming:
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self.log_event_on(instr, EventKind.WAW, cycle)
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found = True
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can_forward = self.has_forwarding and entry.done
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if instr.has_RAW_from(entry.instr) and not can_forward:
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self.log_event_on(instr, EventKind.RAW, cycle)
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found = True
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return found
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def find_structural_hazard(self, instr, cycle):
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"""Detect and log structural hazards"""
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if not self.fus.is_ready_for(instr):
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self.log_event_on(instr, EventKind.STRUCT, cycle)
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return True
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return False
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def try_issue(self, cycle):
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"""Try to issue an instruction"""
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if len(self.instr_queue) == 0 or len(self.scoreboard) >= self.sb_len:
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return
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can_issue = True
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instr = self.instr_queue[0]
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if self.find_data_hazards(instr, cycle):
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can_issue = False
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if self.find_structural_hazard(instr, cycle):
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can_issue = False
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self.issue_manage_last_branch(instr, cycle)
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if not self.iqlen.has(instr):
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can_issue = False
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if can_issue:
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self.iqlen.remove(instr)
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instr = self.instr_queue.pop(0)
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self.log_event_on(instr, EventKind.issue, cycle)
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entry = Entry(instr)
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self.scoreboard.append(entry)
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self.fus.issue(instr)
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self.last_issued = LastIssue(instr, cycle)
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self.ras.resolve(instr)
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def try_execute(self, cycle):
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"""Try to execute instructions"""
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for entry in self.scoreboard:
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entry.cycles_since_issue += 1
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instr = entry.instr
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duration = 1
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if instr.is_load() or instr.is_store():
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duration = 2
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if instr.is_muldiv():
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duration = 2
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if entry.cycles_since_issue == duration:
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self.log_event_on(instr, EventKind.done, cycle)
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entry.done = True
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def try_commit(self, cycle, commit_port):
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"""Try to commit an instruction"""
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if len(self.scoreboard) == 0:
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return
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entry = self.scoreboard[0]
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can_commit = True
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if commit_port > 0:
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if entry.instr.is_store():
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can_commit = False
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if not entry.done:
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can_commit = False
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if can_commit:
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instr = self.scoreboard.pop(0).instr
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self.log_event_on(instr, EventKind.commit, cycle)
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self.retired.append(instr)
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self.commit_manage_last_branch(instr, cycle)
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def run_cycle(self, cycle):
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"""Runs a cycle"""
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self.fus.cycle()
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for commit_port in range(self.commit_width):
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self.try_commit(cycle, commit_port)
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self.try_execute(cycle)
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for _ in range(self.issue_width):
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self.try_issue(cycle)
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self.iqlen.fetch()
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def load_file(self, path):
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"""Fill a model from a trace file"""
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with open(path, "r", encoding="utf8") as file:
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for line in [l.strip() for l in file]:
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found = Model.re_instr.search(line)
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if found:
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address = found.group(2)
|
|
hex_code = found.group(3)
|
|
mnemo = found.group(5)
|
|
instr = Instruction(line, address, hex_code, mnemo)
|
|
self.instr_queue.append(instr)
|
|
|
|
def run(self, cycles=None):
|
|
"""Run until completion"""
|
|
cycle = 0
|
|
while len(self.instr_queue) > 0 or len(self.scoreboard) > 0:
|
|
self.run_cycle(cycle)
|
|
if self.debug:
|
|
print(f"Scoreboard @{cycle}")
|
|
for entry in self.scoreboard:
|
|
print(f" {entry}")
|
|
print(f"iqlen = {self.iqlen.len}")
|
|
print()
|
|
cycle += 1
|
|
|
|
if cycles is not None and cycle > cycles:
|
|
break
|
|
return cycle
|
|
|
|
def write_trace(output_file, instructions):
|
|
"""Write cycle-annotated trace"""
|
|
pattern = re.compile(r"@\s*[0-9]+")
|
|
|
|
lines = []
|
|
for instr in instructions:
|
|
commit_event = instr.events[-1]
|
|
assert commit_event.kind == EventKind.commit
|
|
cycle = commit_event.cycle
|
|
annotated = re.sub(pattern, f"@ {cycle}", instr.line)
|
|
#if EventKind.STRUCT in [e.kind for e in instr.events]:
|
|
# annotated += " #STRUCT"
|
|
#if EventKind.RAW in [e.kind for e in instr.events]:
|
|
# annotated += " #RAW"
|
|
lines.append(f"{annotated}\n")
|
|
|
|
with open(output_file, 'w') as f:
|
|
f.writelines(lines)
|
|
|
|
def print_data(name, value, ts=24, sep='='):
|
|
"Prints 'name = data' with alignment of the '='"
|
|
|
|
spaces = ' ' * (ts - len(name))
|
|
print(f"{name}{spaces} {sep} {value}")
|
|
|
|
def display_scores(scores):
|
|
"""Display a 3D graph of scores against commit/issue-wide"""
|
|
bars = []
|
|
for x, l in enumerate(scores):
|
|
for y, z in enumerate(l):
|
|
bars.append((x, y, z))
|
|
|
|
x, y, z, dx, dy, dz = [], [], [], [], [], []
|
|
for bx, by, bz in bars:
|
|
x.append(bx)
|
|
y.append(by)
|
|
z.append(0)
|
|
dx.append(.5)
|
|
dy.append(.5)
|
|
dz.append(bz)
|
|
|
|
#fig = plt.figure()
|
|
#ax1 = fig.add_subplot(111, projection='3d')
|
|
#ax1.bar3d(x, y, z, dx, dy, dz)
|
|
#ax1.set_xlabel("issue")
|
|
#ax1.set_ylabel("commit")
|
|
#ax1.set_zlabel("CoreMark/MHz")
|
|
#plt.show()
|
|
|
|
def issue_commit_graph(input_file, n = 3):
|
|
"""Plot the issue/commit graph"""
|
|
|
|
r = range(n + 1)
|
|
scores = [[0 for _ in r] for _ in r]
|
|
|
|
if input_file is None:
|
|
scores = [[0, 0, 0, 0, 0, 0], [0, 2.651936045910317, 2.651936045910317, 2.651936045910317, 2.651936045910317, 2.651936045910317], [0, 3.212779150348426, 3.6292766488711137, 3.6292766488711137, 3.6292766488711137, 3.6292766488711137], [0, 3.2550388000624966, 3.900216852056974, 3.914997572701505, 3.914997572701505, 3.914997572701505], [0, 3.2596436557555526, 3.9257869239889134, 3.9420984578510834, 3.9421606193922765, 3.9421606193922765], [0, 3.260695897718491, 3.944757614368385, 3.9623576027736505, 3.9625460150656, 3.9625460150656]] # pylint: disable=line-too-long
|
|
else:
|
|
r = range(1, n + 1)
|
|
for issue in r:
|
|
for commit in r:
|
|
print("running", issue, commit)
|
|
model = Model(issue=issue, commit=commit)
|
|
model.load_file(input_file)
|
|
model.run()
|
|
n_cycles = count_cycles(filter_timed_part(model.retired))
|
|
score = 1000000 / n_cycles
|
|
scores[issue][commit] = score
|
|
print(scores)
|
|
display_scores(scores)
|
|
|
|
def filter_timed_part(all_instructions):
|
|
"Keep only timed part from a trace"
|
|
filtered = []
|
|
re_csrr_minstret = re.compile(r"^csrr\s+\w\w,\s*minstret$")
|
|
accepting = False
|
|
for instr in all_instructions:
|
|
if re_csrr_minstret.search(instr.mnemo):
|
|
accepting = not accepting
|
|
continue
|
|
if accepting:
|
|
filtered.append(instr)
|
|
return filtered
|
|
|
|
def count_cycles(retired):
|
|
start = min(e.cycle for e in retired[0].events)
|
|
end = max(e.cycle for e in retired[-1].events)
|
|
return end - start
|
|
|
|
def print_stats(instructions):
|
|
ecount = defaultdict(lambda: 0)
|
|
|
|
for instr in instructions:
|
|
for e in instr.events:
|
|
ecount[e.kind] += 1
|
|
cycle = e.cycle
|
|
n_instr = len(instructions)
|
|
n_cycles = count_cycles(instructions)
|
|
|
|
print_data("cycle number", n_cycles)
|
|
print_data("Coremark/MHz", 1000000 / n_cycles)
|
|
print_data("instruction number", n_instr)
|
|
for ek, count in ecount.items():
|
|
print_data(f"{ek}/instr", f"{100 * count / n_instr:.2f}%")
|
|
|
|
def main(input_file: str):
|
|
"Entry point"
|
|
|
|
model = Model(debug=True, issue=2, commit=2)
|
|
model.load_file(input_file)
|
|
model.run()
|
|
|
|
write_trace('annotated.log', model.retired)
|
|
print_stats(filter_timed_part(model.retired))
|
|
|
|
if __name__ == "__main__":
|
|
main(sys.argv[1])
|