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7cd183b710
using verible-v0.0-3422-g520ca4b9/bin/verible-verilog-format with default configuration Note: two files are not correctly handled by verible - core/include/std_cache_pkg.sv - core/cache_subsystem/cva6_hpdcache_if_adapter.sv
419 lines
15 KiB
Systemverilog
419 lines
15 KiB
Systemverilog
// Copyright 2020 ETH Zurich and University of Bologna.
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// Copyright and related rights are licensed under the Solderpad Hardware
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// License, Version 0.51 (the "License"); you may not use this file except in
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// compliance with the License. You may obtain a copy of the License at
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// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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// or agreed to in writing, software, hardware and materials distributed under
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// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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// CONDITIONS OF ANY KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations under the License.
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//
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// Authors: Matheus Cavalcante, ETH Zurich
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// Nils Wistoff, ETH Zurich
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// Date: 20.11.2020
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// Description: Functional unit that dispatches CVA6 instructions to accelerators.
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module acc_dispatcher
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import ariane_pkg::*;
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import riscv::*;
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#(
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parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
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parameter type acc_req_t = acc_pkg::accelerator_req_t,
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parameter type acc_resp_t = acc_pkg::accelerator_resp_t,
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parameter type acc_cfg_t = logic,
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parameter acc_cfg_t AccCfg = '0
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) (
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input logic clk_i,
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input logic rst_ni,
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// Interface with the CSR regfile
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input logic acc_cons_en_i, // Accelerator memory consistent mode
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output logic acc_fflags_valid_o,
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output logic [4:0] acc_fflags_o,
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// Interface with the CSRs
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input logic [2:0] fcsr_frm_i,
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output logic dirty_v_state_o,
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// Interface with the issue stage
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input scoreboard_entry_t issue_instr_i,
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input logic issue_instr_hs_i,
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output logic issue_stall_o,
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input fu_data_t fu_data_i,
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input scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i,
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output logic [TRANS_ID_BITS-1:0] acc_trans_id_o,
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output xlen_t acc_result_o,
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output logic acc_valid_o,
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output exception_t acc_exception_o,
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// Interface with the execute stage
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output logic acc_valid_ex_o, // FU executed
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// Interface with the commit stage
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input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i,
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input logic commit_st_barrier_i, // A store barrier was commited
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// Interface with the load/store unit
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output logic acc_stall_st_pending_o,
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input logic acc_no_st_pending_i,
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input dcache_req_i_t [2:0] dcache_req_ports_i,
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// Interface with the controller
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output logic ctrl_halt_o,
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input logic flush_unissued_instr_i,
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input logic flush_ex_i,
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output logic flush_pipeline_o,
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// Interface with cache subsystem
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output dcache_req_i_t [1:0] acc_dcache_req_ports_o,
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input dcache_req_o_t [1:0] acc_dcache_req_ports_i,
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input logic inval_ready_i,
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output logic inval_valid_o,
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output logic [63:0] inval_addr_o,
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// Accelerator interface
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output acc_req_t acc_req_o,
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input acc_resp_t acc_resp_i
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);
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`include "common_cells/registers.svh"
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import cf_math_pkg::idx_width;
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/***********************
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* Common signals *
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***********************/
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logic acc_ready;
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logic acc_valid_d, acc_valid_q;
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/**************************
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* Accelerator issue *
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**************************/
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// Issue accelerator instructions
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`FF(acc_valid_q, acc_valid_d, '0)
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assign acc_valid_ex_o = acc_valid_q;
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assign acc_valid_d = ~issue_instr_i.ex.valid &
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issue_instr_hs_i &
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(issue_instr_i.fu == ACCEL) &
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~flush_unissued_instr_i;
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// Accelerator load/store pending signals
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logic acc_no_ld_pending;
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logic acc_no_st_pending;
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// Stall issue stage in three cases:
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always_comb begin : stall_issue
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unique case (issue_instr_i.fu)
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ACCEL:
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// 1. We're issuing an accelerator instruction but the dispatcher isn't ready yet
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issue_stall_o = ~acc_ready;
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LOAD:
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// 2. We're issuing a scalar load but there is an inflight accelerator store.
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issue_stall_o = acc_cons_en_i & ~acc_no_st_pending;
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STORE:
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// 3. We're issuing a scalar store but there is an inflight accelerator load or store.
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issue_stall_o = acc_cons_en_i & (~acc_no_st_pending | ~acc_no_ld_pending);
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default: issue_stall_o = 1'b0;
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endcase
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end
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/***********************
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* Instruction queue *
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***********************/
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localparam InstructionQueueDepth = 3;
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fu_data_t acc_data;
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fu_data_t acc_insn_queue_o;
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logic acc_insn_queue_pop;
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logic acc_insn_queue_empty;
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logic [idx_width(InstructionQueueDepth)-1:0] acc_insn_queue_usage;
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logic acc_commit;
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logic [ TRANS_ID_BITS-1:0] acc_commit_trans_id;
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assign acc_data = acc_valid_ex_o ? fu_data_i : '0;
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fifo_v3 #(
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.DEPTH (InstructionQueueDepth),
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.FALL_THROUGH(1'b1),
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.dtype (fu_data_t)
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) i_acc_insn_queue (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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.flush_i (flush_ex_i),
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.testmode_i(1'b0),
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.data_i (fu_data_i),
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.push_i (acc_valid_q),
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.full_o ( /* Unused */),
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.data_o (acc_insn_queue_o),
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.pop_i (acc_insn_queue_pop),
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.empty_o (acc_insn_queue_empty),
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.usage_o (acc_insn_queue_usage)
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);
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// We are ready if the instruction queue is able to accept at least one more entry.
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assign acc_ready = acc_insn_queue_usage < (InstructionQueueDepth - 1);
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/**********************************
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* Non-speculative instructions *
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**********************************/
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// Keep track of the instructions that were received by the dispatcher.
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logic [NR_SB_ENTRIES-1:0] insn_pending_d, insn_pending_q;
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`FF(insn_pending_q, insn_pending_d, '0)
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// Only non-speculative instructions can be issued to the accelerators.
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// The following block keeps track of which transaction IDs reached the
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// top of the scoreboard, and are therefore no longer speculative.
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logic [NR_SB_ENTRIES-1:0] insn_ready_d, insn_ready_q;
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`FF(insn_ready_q, insn_ready_d, '0)
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always_comb begin : p_non_speculative_ff
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// Maintain state
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insn_pending_d = insn_pending_q;
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insn_ready_d = insn_ready_q;
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// We received a new instruction
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if (acc_valid_q) insn_pending_d[acc_data.trans_id] = 1'b1;
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// Flush all received instructions
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if (flush_ex_i) insn_pending_d = '0;
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// An accelerator instruction is no longer speculative.
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if (acc_commit && insn_pending_q[acc_commit_trans_id]) begin
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insn_ready_d[acc_commit_trans_id] = 1'b1;
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insn_pending_d[acc_commit_trans_id] = 1'b0;
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end
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// An accelerator instruction was issued.
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if (acc_req_o.req_valid) insn_ready_d[acc_req_o.trans_id] = 1'b0;
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end : p_non_speculative_ff
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/*************************
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* Accelerator request *
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*************************/
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acc_pkg::accelerator_req_t acc_req;
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logic acc_req_valid;
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logic acc_req_ready;
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acc_pkg::accelerator_req_t acc_req_int;
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fall_through_register #(
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.T(acc_pkg::accelerator_req_t)
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) i_accelerator_req_register (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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.clr_i (1'b0),
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.testmode_i(1'b0),
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.data_i (acc_req),
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.valid_i (acc_req_valid),
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.ready_o (acc_req_ready),
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.data_o (acc_req_int),
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.valid_o (acc_req_o.req_valid),
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.ready_i (acc_resp_i.req_ready)
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);
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assign acc_req_o.insn = acc_req_int.insn;
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assign acc_req_o.rs1 = acc_req_int.rs1;
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assign acc_req_o.rs2 = acc_req_int.rs2;
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assign acc_req_o.frm = acc_req_int.frm;
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assign acc_req_o.trans_id = acc_req_int.trans_id;
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assign acc_req_o.store_pending = !acc_no_st_pending_i && acc_cons_en_i;
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assign acc_req_o.acc_cons_en = acc_cons_en_i;
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assign acc_req_o.inval_ready = inval_ready_i;
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always_comb begin : accelerator_req_dispatcher
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// Do not fetch from the instruction queue
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acc_insn_queue_pop = 1'b0;
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// Default values
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acc_req = '0;
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acc_req_valid = 1'b0;
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// Unpack fu_data_t into accelerator_req_t
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if (!acc_insn_queue_empty) begin
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acc_req = '{
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// Instruction is forwarded from the decoder as an immediate
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// -
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// frm rounding information is up to date during a valid request to the accelerator
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// The scoreboard synchronizes it with previous fcsr writes, and future fcsr writes
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// do not take place until the accelerator answers (Ariane commits in-order)
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insn :
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acc_insn_queue_o.imm[
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31
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:
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0
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],
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rs1 : acc_insn_queue_o.operand_a,
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rs2 : acc_insn_queue_o.operand_b,
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frm : fpnew_pkg::roundmode_e'(fcsr_frm_i),
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trans_id: acc_insn_queue_o.trans_id,
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default: '0
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};
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// Wait until the instruction is no longer speculative.
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acc_req_valid = insn_ready_q[acc_insn_queue_o.trans_id] ||
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(acc_commit && insn_pending_q[acc_commit_trans_id]);
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acc_insn_queue_pop = acc_req_valid && acc_req_ready;
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end
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end
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/**************************
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* Accelerator response *
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**************************/
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logic acc_ld_disp;
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logic acc_st_disp;
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// Unpack the accelerator response
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assign acc_trans_id_o = acc_resp_i.trans_id;
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assign acc_result_o = acc_resp_i.result;
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assign acc_valid_o = acc_resp_i.resp_valid;
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assign acc_exception_o = '{cause: riscv::ILLEGAL_INSTR, tval : '0, valid: acc_resp_i.error};
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assign acc_fflags_valid_o = acc_resp_i.fflags_valid;
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assign acc_fflags_o = acc_resp_i.fflags;
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// Always ready to receive responses
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assign acc_req_o.resp_ready = 1'b1;
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// Signal dispatched load/store to issue stage
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assign acc_ld_disp = acc_req_valid && (acc_insn_queue_o.operation == ACCEL_OP_LOAD);
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assign acc_st_disp = acc_req_valid && (acc_insn_queue_o.operation == ACCEL_OP_STORE);
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// Cache invalidation
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assign inval_valid_o = acc_resp_i.inval_valid;
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assign inval_addr_o = acc_resp_i.inval_addr;
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/**************************
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* Accelerator commit *
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**************************/
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// Instruction can be issued to the (in-order) back-end if
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// it reached the top of the scoreboard and it hasn't been
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// issued yet
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always_comb begin : accelerator_commit
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acc_commit = 1'b0;
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if (!commit_instr_i[0].valid && commit_instr_i[0].fu == ACCEL) acc_commit = 1'b1;
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if (commit_instr_i[0].valid && !commit_instr_i[1].valid && commit_instr_i[1].fu == ACCEL)
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acc_commit = 1'b1;
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end
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// Dirty the V state if we are committing anything related to the vector accelerator
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always_comb begin : dirty_v_state
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dirty_v_state_o = 1'b0;
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for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin
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dirty_v_state_o |= commit_ack_i[i] & (commit_instr_i[i].fu == ACCEL);
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end
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end
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assign acc_commit_trans_id = !commit_instr_i[0].valid ? commit_instr_i[0].trans_id
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: commit_instr_i[1].trans_id;
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/**************************
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* Accelerator barriers *
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**************************/
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// On a store barrier (i.e. any barrier that requires preceeding stores to complete
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// before continuing execution), halt execution while there are pending stores in
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// the accelerator pipeline.
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logic wait_acc_store_d, wait_acc_store_q;
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`FF(wait_acc_store_q, wait_acc_store_d, '0)
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// Set on store barrier. Clear when no store is pending.
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assign wait_acc_store_d = (wait_acc_store_q | commit_st_barrier_i) & acc_resp_i.store_pending;
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assign ctrl_halt_o = wait_acc_store_q;
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/**************************
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* Load/Store tracking *
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**************************/
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// Loads
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logic acc_spec_loads_overflow;
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logic [2:0] acc_spec_loads_pending;
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logic acc_disp_loads_overflow;
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logic [2:0] acc_disp_loads_pending;
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assign acc_no_ld_pending = (acc_spec_loads_pending == 3'b0) && (acc_disp_loads_pending == 3'b0);
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// Count speculative loads. These can still be flushed.
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counter #(
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.WIDTH (3),
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.STICKY_OVERFLOW(0)
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) i_acc_spec_loads (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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.clear_i (flush_ex_i),
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.en_i ((acc_valid_d && issue_instr_i.op == ACCEL_OP_LOAD) ^ acc_ld_disp),
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.load_i (1'b0),
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.down_i (acc_ld_disp),
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.d_i ('0),
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.q_o (acc_spec_loads_pending),
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.overflow_o(acc_spec_loads_overflow)
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);
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// Count dispatched loads. These cannot be flushed anymore.
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counter #(
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.WIDTH (3),
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.STICKY_OVERFLOW(0)
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) i_acc_disp_loads (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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.clear_i (1'b0),
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.en_i (acc_ld_disp ^ acc_resp_i.load_complete),
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.load_i (1'b0),
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.down_i (acc_resp_i.load_complete),
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.d_i ('0),
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.q_o (acc_disp_loads_pending),
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.overflow_o(acc_disp_loads_overflow)
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);
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acc_dispatcher_no_load_overflow :
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assert property (
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@(posedge clk_i) disable iff (~rst_ni) (acc_spec_loads_overflow == 1'b0) && (acc_disp_loads_overflow == 1'b0) )
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else $error("[acc_dispatcher] Too many pending loads.");
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// Stores
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logic acc_spec_stores_overflow;
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logic [2:0] acc_spec_stores_pending;
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logic acc_disp_stores_overflow;
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logic [2:0] acc_disp_stores_pending;
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assign acc_no_st_pending = (acc_spec_stores_pending == 3'b0) && (acc_disp_stores_pending == 3'b0);
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// Count speculative stores. These can still be flushed.
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counter #(
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.WIDTH (3),
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.STICKY_OVERFLOW(0)
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) i_acc_spec_stores (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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.clear_i (flush_ex_i),
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.en_i ((acc_valid_d && issue_instr_i.op == ACCEL_OP_STORE) ^ acc_st_disp),
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.load_i (1'b0),
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.down_i (acc_st_disp),
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.d_i ('0),
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.q_o (acc_spec_stores_pending),
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.overflow_o(acc_spec_stores_overflow)
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);
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// Count dispatched stores. These cannot be flushed anymore.
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counter #(
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.WIDTH (3),
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.STICKY_OVERFLOW(0)
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) i_acc_disp_stores (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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.clear_i (1'b0),
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.en_i (acc_st_disp ^ acc_resp_i.store_complete),
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.load_i (1'b0),
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.down_i (acc_resp_i.store_complete),
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.d_i ('0),
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.q_o (acc_disp_stores_pending),
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.overflow_o(acc_disp_stores_overflow)
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);
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acc_dispatcher_no_store_overflow :
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assert property (
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@(posedge clk_i) disable iff (~rst_ni) (acc_spec_stores_overflow == 1'b0) && (acc_disp_stores_overflow == 1'b0) )
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else $error("[acc_dispatcher] Too many pending stores.");
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/**************************
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* Tie Off Unused Signals *
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**************************/
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assign acc_stall_st_pending_o = 1'b0;
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assign flush_pipeline_o = 1'b0;
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assign acc_dcache_req_ports_o = '0;
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endmodule : acc_dispatcher
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