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7cd183b710
using verible-v0.0-3422-g520ca4b9/bin/verible-verilog-format with default configuration Note: two files are not correctly handled by verible - core/include/std_cache_pkg.sv - core/cache_subsystem/cva6_hpdcache_if_adapter.sv
341 lines
13 KiB
Systemverilog
341 lines
13 KiB
Systemverilog
// Copyright 2018 ETH Zurich and University of Bologna.
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// Copyright and related rights are licensed under the Solderpad Hardware
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// License, Version 0.51 (the "License"); you may not use this file except in
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// compliance with the License. You may obtain a copy of the License at
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// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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// or agreed to in writing, software, hardware and materials distributed under
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// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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// CONDITIONS OF ANY KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations under the License.
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//
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// Author: Michael Schaffner <schaffner@iis.ee.ethz.ch>, ETH Zurich
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// Date: 13.09.2018
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// Description: Write-Through Data cache that is compatible with openpiton.
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module wt_dcache
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import ariane_pkg::*;
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import wt_cache_pkg::*;
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#(
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parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
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parameter int unsigned NumPorts = 4, // number of miss ports
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// ID to be used for read and AMO transactions.
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// note that the write buffer uses all IDs up to DCACHE_MAX_TX-1 for write transactions
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parameter logic [CACHE_ID_WIDTH-1:0] RdAmoTxId = 1
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) (
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input logic clk_i, // Clock
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input logic rst_ni, // Asynchronous reset active low
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// Cache management
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input logic enable_i, // from CSR
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input logic flush_i, // high until acknowledged
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output logic flush_ack_o, // send a single cycle acknowledge signal when the cache is flushed
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output logic miss_o, // we missed on a ld/st
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output logic wbuffer_empty_o,
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output logic wbuffer_not_ni_o,
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// AMO interface
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input amo_req_t amo_req_i,
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output amo_resp_t amo_resp_o,
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// Request ports
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input dcache_req_i_t [NumPorts-1:0] req_ports_i,
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output dcache_req_o_t [NumPorts-1:0] req_ports_o,
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output logic [NumPorts-1:0][DCACHE_SET_ASSOC-1:0] miss_vld_bits_o,
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input logic mem_rtrn_vld_i,
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input dcache_rtrn_t mem_rtrn_i,
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output logic mem_data_req_o,
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input logic mem_data_ack_i,
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output dcache_req_t mem_data_o
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);
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// miss unit <-> read controllers
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logic cache_en;
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// miss unit <-> memory
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logic wr_cl_vld;
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logic wr_cl_nc;
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logic [ DCACHE_SET_ASSOC-1:0] wr_cl_we;
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logic [ DCACHE_TAG_WIDTH-1:0] wr_cl_tag;
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logic [ DCACHE_CL_IDX_WIDTH-1:0] wr_cl_idx;
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logic [ DCACHE_OFFSET_WIDTH-1:0] wr_cl_off;
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logic [ DCACHE_LINE_WIDTH-1:0] wr_cl_data;
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logic [DCACHE_USER_LINE_WIDTH-1:0] wr_cl_user;
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logic [ DCACHE_LINE_WIDTH/8-1:0] wr_cl_data_be;
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logic [ DCACHE_SET_ASSOC-1:0] wr_vld_bits;
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logic [ DCACHE_SET_ASSOC-1:0] wr_req;
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logic wr_ack;
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logic [ DCACHE_CL_IDX_WIDTH-1:0] wr_idx;
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logic [ DCACHE_OFFSET_WIDTH-1:0] wr_off;
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riscv::xlen_t wr_data;
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logic [ (riscv::XLEN/8)-1:0] wr_data_be;
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logic [ DCACHE_USER_WIDTH-1:0] wr_user;
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// miss unit <-> controllers/wbuffer
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logic [ NumPorts-1:0] miss_req;
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logic [ NumPorts-1:0] miss_ack;
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logic [ NumPorts-1:0] miss_nc;
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logic [ NumPorts-1:0] miss_we;
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logic [ NumPorts-1:0][ riscv::XLEN-1:0] miss_wdata;
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logic [ NumPorts-1:0][ DCACHE_USER_WIDTH-1:0] miss_wuser;
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logic [ NumPorts-1:0][ riscv::PLEN-1:0] miss_paddr;
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logic [ NumPorts-1:0][ 2:0] miss_size;
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logic [ NumPorts-1:0][ CACHE_ID_WIDTH-1:0] miss_id;
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logic [ NumPorts-1:0] miss_replay;
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logic [ NumPorts-1:0] miss_rtrn_vld;
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logic [ CACHE_ID_WIDTH-1:0] miss_rtrn_id;
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// memory <-> read controllers/miss unit
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logic [ NumPorts-1:0] rd_prio;
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logic [ NumPorts-1:0] rd_tag_only;
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logic [ NumPorts-1:0] rd_req;
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logic [ NumPorts-1:0] rd_ack;
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logic [ NumPorts-1:0][ DCACHE_TAG_WIDTH-1:0] rd_tag;
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logic [ NumPorts-1:0][DCACHE_CL_IDX_WIDTH-1:0] rd_idx;
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logic [ NumPorts-1:0][DCACHE_OFFSET_WIDTH-1:0] rd_off;
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riscv::xlen_t rd_data;
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logic [ DCACHE_USER_WIDTH-1:0] rd_user;
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logic [ DCACHE_SET_ASSOC-1:0] rd_vld_bits;
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logic [ DCACHE_SET_ASSOC-1:0] rd_hit_oh;
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// miss unit <-> wbuffer
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logic [ DCACHE_MAX_TX-1:0][ riscv::PLEN-1:0] tx_paddr;
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logic [ DCACHE_MAX_TX-1:0] tx_vld;
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// wbuffer <-> memory
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wbuffer_t [ DCACHE_WBUF_DEPTH-1:0] wbuffer_data;
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///////////////////////////////////////////////////////
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// miss handling unit
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///////////////////////////////////////////////////////
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wt_dcache_missunit #(
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.CVA6Cfg (CVA6Cfg),
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.AmoTxId (RdAmoTxId),
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.NumPorts(NumPorts)
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) i_wt_dcache_missunit (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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.enable_i (enable_i),
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.flush_i (flush_i),
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.flush_ack_o (flush_ack_o),
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.miss_o (miss_o),
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.wbuffer_empty_i(wbuffer_empty_o),
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.cache_en_o (cache_en),
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// amo interface
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.amo_req_i (amo_req_i),
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.amo_resp_o (amo_resp_o),
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// miss handling interface
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.miss_req_i (miss_req),
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.miss_ack_o (miss_ack),
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.miss_nc_i (miss_nc),
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.miss_we_i (miss_we),
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.miss_wdata_i (miss_wdata),
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.miss_wuser_i (miss_wuser),
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.miss_paddr_i (miss_paddr),
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.miss_vld_bits_i(miss_vld_bits_o),
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.miss_size_i (miss_size),
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.miss_id_i (miss_id),
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.miss_replay_o (miss_replay),
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.miss_rtrn_vld_o(miss_rtrn_vld),
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.miss_rtrn_id_o (miss_rtrn_id),
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// from writebuffer
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.tx_paddr_i (tx_paddr),
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.tx_vld_i (tx_vld),
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// cache memory interface
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.wr_cl_vld_o (wr_cl_vld),
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.wr_cl_nc_o (wr_cl_nc),
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.wr_cl_we_o (wr_cl_we),
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.wr_cl_tag_o (wr_cl_tag),
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.wr_cl_idx_o (wr_cl_idx),
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.wr_cl_off_o (wr_cl_off),
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.wr_cl_data_o (wr_cl_data),
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.wr_cl_user_o (wr_cl_user),
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.wr_cl_data_be_o(wr_cl_data_be),
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.wr_vld_bits_o (wr_vld_bits),
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// memory interface
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.mem_rtrn_vld_i (mem_rtrn_vld_i),
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.mem_rtrn_i (mem_rtrn_i),
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.mem_data_req_o (mem_data_req_o),
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.mem_data_ack_i (mem_data_ack_i),
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.mem_data_o (mem_data_o)
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);
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///////////////////////////////////////////////////////
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// read controllers (LD unit and PTW/MMU)
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///////////////////////////////////////////////////////
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// note: last read port is used by the write buffer
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for (genvar k = 0; k < NumPorts - 1; k++) begin : gen_rd_ports
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// set these to high prio ports
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assign rd_prio[k] = 1'b1;
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wt_dcache_ctrl #(
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.CVA6Cfg(CVA6Cfg),
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.RdTxId (RdAmoTxId)
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) i_wt_dcache_ctrl (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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.cache_en_i (cache_en),
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// reqs from core
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.req_port_i (req_ports_i[k]),
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.req_port_o (req_ports_o[k]),
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// miss interface
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.miss_req_o (miss_req[k]),
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.miss_ack_i (miss_ack[k]),
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.miss_we_o (miss_we[k]),
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.miss_wdata_o (miss_wdata[k]),
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.miss_wuser_o (miss_wuser[k]),
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.miss_vld_bits_o(miss_vld_bits_o[k]),
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.miss_paddr_o (miss_paddr[k]),
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.miss_nc_o (miss_nc[k]),
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.miss_size_o (miss_size[k]),
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.miss_id_o (miss_id[k]),
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.miss_replay_i (miss_replay[k]),
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.miss_rtrn_vld_i(miss_rtrn_vld[k]),
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// used to detect readout mux collisions
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.wr_cl_vld_i (wr_cl_vld),
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// cache mem interface
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.rd_tag_o (rd_tag[k]),
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.rd_idx_o (rd_idx[k]),
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.rd_off_o (rd_off[k]),
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.rd_req_o (rd_req[k]),
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.rd_tag_only_o (rd_tag_only[k]),
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.rd_ack_i (rd_ack[k]),
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.rd_data_i (rd_data),
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.rd_user_i (rd_user),
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.rd_vld_bits_i (rd_vld_bits),
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.rd_hit_oh_i (rd_hit_oh)
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);
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end
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///////////////////////////////////////////////////////
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// store unit controller
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///////////////////////////////////////////////////////
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// set read port to low priority
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assign rd_prio[NumPorts-1] = 1'b0;
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wt_dcache_wbuffer #(
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.CVA6Cfg(CVA6Cfg)
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) i_wt_dcache_wbuffer (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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.empty_o (wbuffer_empty_o),
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.not_ni_o (wbuffer_not_ni_o),
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// TODO: fix this
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.cache_en_i (cache_en),
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// .cache_en_i ( '0 ),
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// request ports from core (store unit)
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.req_port_i (req_ports_i[NumPorts-1]),
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.req_port_o (req_ports_o[NumPorts-1]),
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// miss unit interface
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.miss_req_o (miss_req[NumPorts-1]),
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.miss_ack_i (miss_ack[NumPorts-1]),
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.miss_we_o (miss_we[NumPorts-1]),
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.miss_wdata_o (miss_wdata[NumPorts-1]),
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.miss_wuser_o (miss_wuser[NumPorts-1]),
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.miss_vld_bits_o(miss_vld_bits_o[NumPorts-1]),
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.miss_paddr_o (miss_paddr[NumPorts-1]),
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.miss_nc_o (miss_nc[NumPorts-1]),
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.miss_size_o (miss_size[NumPorts-1]),
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.miss_id_o (miss_id[NumPorts-1]),
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.miss_rtrn_vld_i(miss_rtrn_vld[NumPorts-1]),
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.miss_rtrn_id_i (miss_rtrn_id),
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// cache read interface
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.rd_tag_o (rd_tag[NumPorts-1]),
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.rd_idx_o (rd_idx[NumPorts-1]),
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.rd_off_o (rd_off[NumPorts-1]),
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.rd_req_o (rd_req[NumPorts-1]),
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.rd_tag_only_o (rd_tag_only[NumPorts-1]),
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.rd_ack_i (rd_ack[NumPorts-1]),
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.rd_data_i (rd_data),
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.rd_vld_bits_i (rd_vld_bits),
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.rd_hit_oh_i (rd_hit_oh),
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// incoming invalidations/cache refills
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.wr_cl_vld_i (wr_cl_vld),
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.wr_cl_idx_i (wr_cl_idx),
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// single word write interface
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.wr_req_o (wr_req),
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.wr_ack_i (wr_ack),
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.wr_idx_o (wr_idx),
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.wr_off_o (wr_off),
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.wr_data_o (wr_data),
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.wr_user_o (wr_user),
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.wr_data_be_o (wr_data_be),
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// write buffer forwarding
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.wbuffer_data_o (wbuffer_data),
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.tx_paddr_o (tx_paddr),
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.tx_vld_o (tx_vld)
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);
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///////////////////////////////////////////////////////
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// memory arrays, arbitration and tag comparison
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///////////////////////////////////////////////////////
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wt_dcache_mem #(
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.CVA6Cfg (CVA6Cfg),
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.NumPorts(NumPorts)
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) i_wt_dcache_mem (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// read ports
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.rd_prio_i (rd_prio),
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.rd_tag_i (rd_tag),
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.rd_idx_i (rd_idx),
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.rd_off_i (rd_off),
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.rd_req_i (rd_req),
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.rd_tag_only_i (rd_tag_only),
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.rd_ack_o (rd_ack),
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.rd_vld_bits_o (rd_vld_bits),
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.rd_hit_oh_o (rd_hit_oh),
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.rd_data_o (rd_data),
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.rd_user_o (rd_user),
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// cacheline write port
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.wr_cl_vld_i (wr_cl_vld),
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.wr_cl_nc_i (wr_cl_nc),
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.wr_cl_we_i (wr_cl_we),
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.wr_cl_tag_i (wr_cl_tag),
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.wr_cl_idx_i (wr_cl_idx),
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.wr_cl_off_i (wr_cl_off),
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.wr_cl_data_i (wr_cl_data),
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.wr_cl_user_i (wr_cl_user),
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.wr_cl_data_be_i(wr_cl_data_be),
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.wr_vld_bits_i (wr_vld_bits),
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// single word write port
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.wr_req_i (wr_req),
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.wr_ack_o (wr_ack),
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.wr_idx_i (wr_idx),
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.wr_off_i (wr_off),
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.wr_data_i (wr_data),
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.wr_user_i (wr_user),
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.wr_data_be_i (wr_data_be),
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// write buffer forwarding
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.wbuffer_data_i (wbuffer_data)
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);
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///////////////////////////////////////////////////////
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// assertions
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///////////////////////////////////////////////////////
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// check for concurrency issues
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//pragma translate_off
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`ifndef VERILATOR
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flush :
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assert property (
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@(posedge clk_i) disable iff (!rst_ni) flush_i |-> flush_ack_o |-> wbuffer_empty_o)
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else $fatal(1, "[l1 dcache] flushed cache implies flushed wbuffer");
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initial begin
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// assert wrong parameterizations
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assert (DCACHE_INDEX_WIDTH <= 12)
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else $fatal(1, "[l1 dcache] cache index width can be maximum 12bit since VM uses 4kB pages");
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end
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`endif
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//pragma translate_on
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endmodule // wt_dcache
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