mirror of
https://github.com/openhwgroup/cva6.git
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7cd183b710
using verible-v0.0-3422-g520ca4b9/bin/verible-verilog-format with default configuration Note: two files are not correctly handled by verible - core/include/std_cache_pkg.sv - core/cache_subsystem/cva6_hpdcache_if_adapter.sv
71 lines
2.2 KiB
Systemverilog
71 lines
2.2 KiB
Systemverilog
//Copyright (C) 2018 to present,
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// Copyright and related rights are licensed under the Solderpad Hardware
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// License, Version 2.0 (the "License"); you may not use this file except in
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// compliance with the License. You may obtain a copy of the License at
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// http://solderpad.org/licenses/SHL-2.0. Unless required by applicable law
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// or agreed to in writing, software, hardware and materials distributed under
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// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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// CONDITIONS OF ANY KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations under the License.
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//
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// Author: Florian Zaruba, ETH Zurich
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// Date: 08.02.2018
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// Migrated: Luis Vitorio Cargnini, IEEE
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// Date: 09.06.2018
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// return address stack
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module ras #(
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parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
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parameter int unsigned DEPTH = 2
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) (
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input logic clk_i,
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input logic rst_ni,
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input logic flush_i,
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input logic push_i,
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input logic pop_i,
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input logic [riscv::VLEN-1:0] data_i,
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output ariane_pkg::ras_t data_o
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);
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ariane_pkg::ras_t [DEPTH-1:0] stack_d, stack_q;
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assign data_o = stack_q[0];
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always_comb begin
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stack_d = stack_q;
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// push on the stack
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if (push_i) begin
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stack_d[0].ra = data_i;
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// mark the new return address as valid
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stack_d[0].valid = 1'b1;
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stack_d[DEPTH-1:1] = stack_q[DEPTH-2:0];
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end
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if (pop_i) begin
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stack_d[DEPTH-2:0] = stack_q[DEPTH-1:1];
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// we popped the value so invalidate the end of the stack
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stack_d[DEPTH-1].valid = 1'b0;
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stack_d[DEPTH-1].ra = 'b0;
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end
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// leave everything untouched and just push the latest value to the
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// top of the stack
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if (pop_i && push_i) begin
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stack_d = stack_q;
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stack_d[0].ra = data_i;
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stack_d[0].valid = 1'b1;
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end
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if (flush_i) begin
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stack_d = '0;
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end
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end
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (~rst_ni) begin
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stack_q <= '0;
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end else begin
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stack_q <= stack_d;
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end
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end
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endmodule
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