mirror of
https://github.com/openhwgroup/cva6.git
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691 lines
25 KiB
Systemverilog
691 lines
25 KiB
Systemverilog
// Copyright 2018 ETH Zurich and University of Bologna.
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// Copyright and related rights are licensed under the Solderpad Hardware
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// License, Version 0.51 (the "License"); you may not use this file except in
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// compliance with the License. You may obtain a copy of the License at
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// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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// or agreed to in writing, software, hardware and materials distributed under
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// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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// CONDITIONS OF ANY KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations under the License.
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//
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// Author: Florian Zaruba, ETH Zurich
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// Date: 19.04.2017
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// Description: Load Store Unit, handles address calculation and memory interface signals
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module load_store_unit
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import ariane_pkg::*;
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#(
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parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
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parameter type dcache_req_i_t = logic,
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parameter type dcache_req_o_t = logic,
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parameter type exception_t = logic,
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parameter type fu_data_t = logic,
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parameter type icache_areq_t = logic,
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parameter type icache_arsp_t = logic,
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parameter type icache_dreq_t = logic,
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parameter type icache_drsp_t = logic,
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parameter type lsu_ctrl_t = logic
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) (
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// Subsystem Clock - SUBSYSTEM
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input logic clk_i,
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// Asynchronous reset active low - SUBSYSTEM
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input logic rst_ni,
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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input logic flush_i,
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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input logic stall_st_pending_i,
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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output logic no_st_pending_o,
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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input logic amo_valid_commit_i,
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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input logic [31:0] tinst_i,
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// FU data needed to execute instruction - ISSUE_STAGE
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input fu_data_t fu_data_i,
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// Load Store Unit is ready - ISSUE_STAGE
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output logic lsu_ready_o,
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// Load Store Unit instruction is valid - ISSUE_STAGE
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input logic lsu_valid_i,
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// Load transaction ID - ISSUE_STAGE
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output logic [CVA6Cfg.TRANS_ID_BITS-1:0] load_trans_id_o,
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// Load result - ISSUE_STAGE
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output logic [CVA6Cfg.XLEN-1:0] load_result_o,
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// Load result is valid - ISSUE_STAGE
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output logic load_valid_o,
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// Load exception - ISSUE_STAGE
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output exception_t load_exception_o,
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// Store transaction ID - ISSUE_STAGE
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output logic [CVA6Cfg.TRANS_ID_BITS-1:0] store_trans_id_o,
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// Store result - ISSUE_STAGE
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output logic [CVA6Cfg.XLEN-1:0] store_result_o,
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// Store result is valid - ISSUE_STAGE
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output logic store_valid_o,
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// Store exception - ISSUE_STAGE
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output exception_t store_exception_o,
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// Commit the first pending store - TO_BE_COMPLETED
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input logic commit_i,
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// Commit queue is ready to accept another commit request - TO_BE_COMPLETED
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output logic commit_ready_o,
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// Commit transaction ID - TO_BE_COMPLETED
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input logic [CVA6Cfg.TRANS_ID_BITS-1:0] commit_tran_id_i,
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// Enable virtual memory translation - TO_BE_COMPLETED
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input logic enable_translation_i,
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// Enable G-Stage memory translation - TO_BE_COMPLETED
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input logic enable_g_translation_i,
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// Enable virtual memory translation for load/stores - TO_BE_COMPLETED
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input logic en_ld_st_translation_i,
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// Enable G-Stage memory translation for load/stores - TO_BE_COMPLETED
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input logic en_ld_st_g_translation_i,
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// Instruction cache input request - CACHES
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input icache_arsp_t icache_areq_i,
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// Instruction cache output request - CACHES
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output icache_areq_t icache_areq_o,
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// Current privilege mode - CSR_REGFILE
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input riscv::priv_lvl_t priv_lvl_i,
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// Current virtualization mode - CSR_REGFILE
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input logic v_i,
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// Privilege level at which load and stores should happen - CSR_REGFILE
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input riscv::priv_lvl_t ld_st_priv_lvl_i,
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// Virtualization mode at which load and stores should happen - CSR_REGFILE
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input logic ld_st_v_i,
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// Instruction is a hyp load/store - CSR_REGFILE
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output logic csr_hs_ld_st_inst_o,
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// Supervisor User Memory - CSR_REGFILE
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input logic sum_i,
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// Virtual Supervisor User Memory - CSR_REGFILE
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input logic vs_sum_i,
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// Make Executable Readable - CSR_REGFILE
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input logic mxr_i,
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// Make Executable Readable Virtual Supervisor - CSR_REGFILE
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input logic vmxr_i,
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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input logic [ CVA6Cfg.PPNW-1:0] satp_ppn_i,
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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input logic [CVA6Cfg.ASID_WIDTH-1:0] asid_i,
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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input logic [ CVA6Cfg.PPNW-1:0] vsatp_ppn_i,
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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input logic [CVA6Cfg.ASID_WIDTH-1:0] vs_asid_i,
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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input logic [ CVA6Cfg.PPNW-1:0] hgatp_ppn_i,
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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input logic [CVA6Cfg.VMID_WIDTH-1:0] vmid_i,
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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input logic [CVA6Cfg.ASID_WIDTH-1:0] asid_to_be_flushed_i,
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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input logic [CVA6Cfg.VMID_WIDTH-1:0] vmid_to_be_flushed_i,
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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input logic [ CVA6Cfg.VLEN-1:0] vaddr_to_be_flushed_i,
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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input logic [ CVA6Cfg.GPLEN-1:0] gpaddr_to_be_flushed_i,
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// TLB flush - CONTROLLER
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input logic flush_tlb_i,
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input logic flush_tlb_vvma_i,
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input logic flush_tlb_gvma_i,
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// Instruction TLB miss - PERF_COUNTERS
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output logic itlb_miss_o,
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// Data TLB miss - PERF_COUNTERS
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output logic dtlb_miss_o,
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// Data cache request output - CACHES
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input dcache_req_o_t [ 2:0] dcache_req_ports_i,
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// Data cache request input - CACHES
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output dcache_req_i_t [ 2:0] dcache_req_ports_o,
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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input logic dcache_wbuffer_empty_i,
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// TO_BE_COMPLETED - TO_BE_COMPLETED
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input logic dcache_wbuffer_not_ni_i,
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// AMO request - CACHE
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output amo_req_t amo_req_o,
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// AMO response - CACHE
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input amo_resp_t amo_resp_i,
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// PMP configuration - CSR_REGFILE
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input riscv::pmpcfg_t [15:0] pmpcfg_i,
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// PMP address - CSR_REGFILE
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input logic [15:0][CVA6Cfg.PLEN-3:0] pmpaddr_i,
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// RVFI inforamtion - RVFI
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output lsu_ctrl_t rvfi_lsu_ctrl_o,
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// RVFI information - RVFI
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output [CVA6Cfg.PLEN-1:0] rvfi_mem_paddr_o
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);
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// data is misaligned
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logic data_misaligned;
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// --------------------------------------
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// 1st register stage - (stall registers)
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// --------------------------------------
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// those are the signals which are always correct
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// e.g.: they keep the value in the stall case
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lsu_ctrl_t lsu_ctrl;
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logic pop_st;
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logic pop_ld;
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// ------------------------------
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// Address Generation Unit (AGU)
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// ------------------------------
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// virtual address as calculated by the AGU in the first cycle
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logic [ CVA6Cfg.VLEN-1:0] vaddr_i;
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logic [ CVA6Cfg.XLEN-1:0] vaddr_xlen;
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logic overflow;
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logic g_overflow;
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logic [(CVA6Cfg.XLEN/8)-1:0] be_i;
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assign vaddr_xlen = $unsigned($signed(fu_data_i.imm) + $signed(fu_data_i.operand_a));
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assign vaddr_i = vaddr_xlen[CVA6Cfg.VLEN-1:0];
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// we work with SV39 or SV32, so if VM is enabled, check that all bits [XLEN-1:38] or [XLEN-1:31] are equal
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assign overflow = (CVA6Cfg.IS_XLEN64 && (!((&vaddr_xlen[CVA6Cfg.XLEN-1:CVA6Cfg.SV-1]) == 1'b1 || (|vaddr_xlen[CVA6Cfg.XLEN-1:CVA6Cfg.SV-1]) == 1'b0)));
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if (CVA6Cfg.RVH) begin : gen_g_overflow_hyp
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assign g_overflow = (CVA6Cfg.IS_XLEN64 && (!((|vaddr_xlen[CVA6Cfg.XLEN-1:CVA6Cfg.SVX]) == 1'b0)));
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end else begin : gen_g_overflow_no_hyp
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assign g_overflow = 1'b0;
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end
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logic st_valid_i;
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logic ld_valid_i;
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logic ld_translation_req;
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logic st_translation_req;
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logic [CVA6Cfg.VLEN-1:0] ld_vaddr;
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logic [ 31:0] ld_tinst;
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logic ld_hs_ld_st_inst;
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logic ld_hlvx_inst;
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logic [CVA6Cfg.VLEN-1:0] st_vaddr;
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logic [ 31:0] st_tinst;
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logic st_hs_ld_st_inst;
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logic st_hlvx_inst;
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logic translation_req;
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logic translation_valid;
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logic [CVA6Cfg.VLEN-1:0] mmu_vaddr;
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logic [CVA6Cfg.PLEN-1:0] mmu_paddr, mmu_vaddr_plen, fetch_vaddr_plen;
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logic [ 31:0] mmu_tinst;
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logic mmu_hs_ld_st_inst;
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logic mmu_hlvx_inst;
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exception_t mmu_exception;
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logic dtlb_hit;
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logic [ CVA6Cfg.PPNW-1:0] dtlb_ppn;
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logic ld_valid;
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logic [CVA6Cfg.TRANS_ID_BITS-1:0] ld_trans_id;
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logic [ CVA6Cfg.XLEN-1:0] ld_result;
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logic st_valid;
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logic [CVA6Cfg.TRANS_ID_BITS-1:0] st_trans_id;
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logic [ CVA6Cfg.XLEN-1:0] st_result;
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logic [ 11:0] page_offset;
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logic page_offset_matches;
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exception_t misaligned_exception;
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exception_t ld_ex;
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exception_t st_ex;
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logic hs_ld_st_inst;
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logic hlvx_inst;
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logic [2:0] enable_translation, en_ld_st_translation, flush_tlb;
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logic [1:0] sum, mxr;
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logic [CVA6Cfg.PPNW-1:0] satp_ppn[2:0];
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logic [CVA6Cfg.ASID_WIDTH-1:0] asid[2:0], asid_to_be_flushed[1:0];
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logic [CVA6Cfg.VLEN-1:0] vaddr_to_be_flushed[1:0];
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// -------------------
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// MMU e.g.: TLBs/PTW
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// -------------------
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if (CVA6Cfg.MmuPresent) begin : gen_mmu
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localparam HYP_EXT = CVA6Cfg.RVH ? 1 : 0;
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cva6_mmu #(
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.CVA6Cfg (CVA6Cfg),
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.exception_t (exception_t),
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.icache_areq_t (icache_areq_t),
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.icache_arsp_t (icache_arsp_t),
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.icache_dreq_t (icache_dreq_t),
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.icache_drsp_t (icache_drsp_t),
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.dcache_req_i_t(dcache_req_i_t),
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.dcache_req_o_t(dcache_req_o_t),
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.HYP_EXT (HYP_EXT)
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) i_cva6_mmu (
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.clk_i(clk_i),
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.rst_ni(rst_ni),
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.flush_i(flush_i),
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.icache_areq_i(icache_areq_i),
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.icache_areq_o(icache_areq_o),
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// misaligned bypass
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.misaligned_ex_i(misaligned_exception),
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.lsu_req_i(translation_req),
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.lsu_vaddr_i(mmu_vaddr),
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.lsu_tinst_i(mmu_tinst),
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.lsu_is_store_i(st_translation_req),
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.csr_hs_ld_st_inst_o(csr_hs_ld_st_inst_o),
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.lsu_dtlb_hit_o(dtlb_hit), // send in the same cycle as the request
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.lsu_dtlb_ppn_o(dtlb_ppn), // send in the same cycle as the request
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.lsu_valid_o (translation_valid),
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.lsu_paddr_o (mmu_paddr),
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.lsu_exception_o(mmu_exception),
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.priv_lvl_i (priv_lvl_i),
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.ld_st_priv_lvl_i(ld_st_priv_lvl_i),
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.hlvx_inst_i (mmu_hlvx_inst),
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.hs_ld_st_inst_i(mmu_hs_ld_st_inst),
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.itlb_miss_o(itlb_miss_o),
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.dtlb_miss_o(dtlb_miss_o),
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.req_port_i(dcache_req_ports_i[0]),
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.req_port_o(dcache_req_ports_o[0]),
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.pmpcfg_i,
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.pmpaddr_i,
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.*
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);
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end else begin : gen_no_mmu
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if (CVA6Cfg.VLEN > CVA6Cfg.PLEN) begin
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assign mmu_vaddr_plen = mmu_vaddr[CVA6Cfg.PLEN-1:0];
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assign fetch_vaddr_plen = icache_areq_i.fetch_vaddr[CVA6Cfg.PLEN-1:0];
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end else begin
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assign mmu_vaddr_plen = {{{CVA6Cfg.PLEN - CVA6Cfg.VLEN} {1'b0}}, mmu_vaddr};
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assign fetch_vaddr_plen = {{{CVA6Cfg.PLEN - CVA6Cfg.VLEN} {1'b0}}, icache_areq_i.fetch_vaddr};
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end
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assign icache_areq_o.fetch_valid = icache_areq_i.fetch_req;
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assign icache_areq_o.fetch_paddr = fetch_vaddr_plen;
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assign icache_areq_o.fetch_exception = '0;
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assign dcache_req_ports_o[0].address_index = '0;
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assign dcache_req_ports_o[0].address_tag = '0;
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assign dcache_req_ports_o[0].data_wdata = '0;
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assign dcache_req_ports_o[0].data_req = 1'b0;
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assign dcache_req_ports_o[0].data_be = '1;
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assign dcache_req_ports_o[0].data_size = 2'b11;
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assign dcache_req_ports_o[0].data_we = 1'b0;
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assign dcache_req_ports_o[0].kill_req = '0;
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assign dcache_req_ports_o[0].tag_valid = 1'b0;
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assign itlb_miss_o = 1'b0;
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assign dtlb_miss_o = 1'b0;
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assign dtlb_ppn = mmu_vaddr_plen[CVA6Cfg.PLEN-1:12];
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assign dtlb_hit = 1'b1;
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (~rst_ni) begin
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mmu_paddr <= '0;
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translation_valid <= '0;
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mmu_exception <= '0;
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end else begin
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mmu_paddr <= mmu_vaddr_plen;
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translation_valid <= translation_req;
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mmu_exception <= misaligned_exception;
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end
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end
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end
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logic store_buffer_empty;
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// ------------------
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// Store Unit
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// ------------------
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store_unit #(
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.CVA6Cfg(CVA6Cfg),
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.dcache_req_i_t(dcache_req_i_t),
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.dcache_req_o_t(dcache_req_o_t),
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.exception_t(exception_t),
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.lsu_ctrl_t(lsu_ctrl_t)
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) i_store_unit (
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.clk_i,
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.rst_ni,
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.flush_i,
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.stall_st_pending_i,
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.no_st_pending_o,
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.store_buffer_empty_o(store_buffer_empty),
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.valid_i (st_valid_i),
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.lsu_ctrl_i(lsu_ctrl),
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.pop_st_o (pop_st),
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.commit_i,
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.commit_ready_o,
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.amo_valid_commit_i,
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.valid_o (st_valid),
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.trans_id_o (st_trans_id),
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.result_o (st_result),
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.ex_o (st_ex),
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// MMU port
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.translation_req_o (st_translation_req),
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.vaddr_o (st_vaddr),
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.rvfi_mem_paddr_o (rvfi_mem_paddr_o),
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.tinst_o (st_tinst),
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.hs_ld_st_inst_o (st_hs_ld_st_inst),
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.hlvx_inst_o (st_hlvx_inst),
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.paddr_i (mmu_paddr),
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.ex_i (mmu_exception),
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.dtlb_hit_i (dtlb_hit),
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// Load Unit
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.page_offset_i (page_offset),
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.page_offset_matches_o(page_offset_matches),
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// AMOs
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.amo_req_o,
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.amo_resp_i,
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// to memory arbiter
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.req_port_i (dcache_req_ports_i[2]),
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.req_port_o (dcache_req_ports_o[2])
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);
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// ------------------
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// Load Unit
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// ------------------
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load_unit #(
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.CVA6Cfg(CVA6Cfg),
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.dcache_req_i_t(dcache_req_i_t),
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.dcache_req_o_t(dcache_req_o_t),
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.exception_t(exception_t),
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.lsu_ctrl_t(lsu_ctrl_t)
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) i_load_unit (
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.valid_i (ld_valid_i),
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.lsu_ctrl_i(lsu_ctrl),
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.pop_ld_o (pop_ld),
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.valid_o (ld_valid),
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.trans_id_o (ld_trans_id),
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.result_o (ld_result),
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.ex_o (ld_ex),
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// MMU port
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.translation_req_o (ld_translation_req),
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.vaddr_o (ld_vaddr),
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.tinst_o (ld_tinst),
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.hs_ld_st_inst_o (ld_hs_ld_st_inst),
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.hlvx_inst_o (ld_hlvx_inst),
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|
.paddr_i (mmu_paddr),
|
|
.ex_i (mmu_exception),
|
|
.dtlb_hit_i (dtlb_hit),
|
|
.dtlb_ppn_i (dtlb_ppn),
|
|
// to store unit
|
|
.page_offset_o (page_offset),
|
|
.page_offset_matches_i(page_offset_matches),
|
|
.store_buffer_empty_i (store_buffer_empty),
|
|
// to memory arbiter
|
|
.req_port_i (dcache_req_ports_i[1]),
|
|
.req_port_o (dcache_req_ports_o[1]),
|
|
.dcache_wbuffer_not_ni_i,
|
|
.commit_tran_id_i,
|
|
.*
|
|
);
|
|
|
|
// ----------------------------
|
|
// Output Pipeline Register
|
|
// ----------------------------
|
|
|
|
// amount of pipeline registers inserted for load/store return path
|
|
// can be tuned to trade-off IPC vs. cycle time
|
|
|
|
shift_reg #(
|
|
.dtype(logic [$bits(ld_valid) + $bits(ld_trans_id) + $bits(ld_result) + $bits(ld_ex) - 1:0]),
|
|
.Depth(CVA6Cfg.NrLoadPipeRegs)
|
|
) i_pipe_reg_load (
|
|
.clk_i,
|
|
.rst_ni,
|
|
.d_i({ld_valid, ld_trans_id, ld_result, ld_ex}),
|
|
.d_o({load_valid_o, load_trans_id_o, load_result_o, load_exception_o})
|
|
);
|
|
|
|
shift_reg #(
|
|
.dtype(logic [$bits(st_valid) + $bits(st_trans_id) + $bits(st_result) + $bits(st_ex) - 1:0]),
|
|
.Depth(CVA6Cfg.NrStorePipeRegs)
|
|
) i_pipe_reg_store (
|
|
.clk_i,
|
|
.rst_ni,
|
|
.d_i({st_valid, st_trans_id, st_result, st_ex}),
|
|
.d_o({store_valid_o, store_trans_id_o, store_result_o, store_exception_o})
|
|
);
|
|
|
|
// determine whether this is a load or store
|
|
always_comb begin : which_op
|
|
|
|
ld_valid_i = 1'b0;
|
|
st_valid_i = 1'b0;
|
|
|
|
translation_req = 1'b0;
|
|
mmu_vaddr = {CVA6Cfg.VLEN{1'b0}};
|
|
mmu_tinst = {32{1'b0}};
|
|
mmu_hs_ld_st_inst = 1'b0;
|
|
mmu_hlvx_inst = 1'b0;
|
|
|
|
// check the operation to activate the right functional unit accordingly
|
|
unique case (lsu_ctrl.fu)
|
|
// all loads go here
|
|
LOAD: begin
|
|
ld_valid_i = lsu_ctrl.valid;
|
|
translation_req = ld_translation_req;
|
|
mmu_vaddr = ld_vaddr;
|
|
if (CVA6Cfg.RVH) begin
|
|
mmu_tinst = ld_tinst;
|
|
mmu_hs_ld_st_inst = ld_hs_ld_st_inst;
|
|
mmu_hlvx_inst = ld_hlvx_inst;
|
|
end
|
|
end
|
|
// all stores go here
|
|
STORE: begin
|
|
st_valid_i = lsu_ctrl.valid;
|
|
translation_req = st_translation_req;
|
|
mmu_vaddr = st_vaddr;
|
|
if (CVA6Cfg.RVH) begin
|
|
mmu_tinst = st_tinst;
|
|
mmu_hs_ld_st_inst = st_hs_ld_st_inst;
|
|
mmu_hlvx_inst = st_hlvx_inst;
|
|
end
|
|
end
|
|
// not relevant for the LSU
|
|
default: ;
|
|
endcase
|
|
end
|
|
|
|
// ------------------------
|
|
// Hypervisor Load/Store
|
|
// ------------------------
|
|
// determine whether this is a hypervisor load or store
|
|
if (CVA6Cfg.RVH) begin
|
|
always_comb begin : hyp_ld_st
|
|
// check the operator to activate the right functional unit accordingly
|
|
hs_ld_st_inst = 1'b0;
|
|
hlvx_inst = 1'b0;
|
|
case (lsu_ctrl.operation)
|
|
// all loads go here
|
|
HLV_B, HLV_BU, HLV_H, HLV_HU, HLV_W, HSV_B, HSV_H, HSV_W, HLV_WU, HLV_D, HSV_D: begin
|
|
hs_ld_st_inst = 1'b1;
|
|
end
|
|
HLVX_WU, HLVX_HU: begin
|
|
hs_ld_st_inst = 1'b1;
|
|
hlvx_inst = 1'b1;
|
|
end
|
|
default: ;
|
|
endcase
|
|
end
|
|
end else begin
|
|
assign hs_ld_st_inst = 1'b0;
|
|
assign hlvx_inst = 1'b0;
|
|
end
|
|
|
|
// ---------------
|
|
// Byte Enable
|
|
// ---------------
|
|
// we can generate the byte enable from the virtual address since the last
|
|
// 12 bit are the same anyway
|
|
// and we can always generate the byte enable from the address at hand
|
|
|
|
if (CVA6Cfg.IS_XLEN64) begin : gen_8b_be
|
|
assign be_i = be_gen(vaddr_i[2:0], extract_transfer_size(fu_data_i.operation));
|
|
end else begin : gen_4b_be
|
|
assign be_i = be_gen_32(vaddr_i[1:0], extract_transfer_size(fu_data_i.operation));
|
|
end
|
|
|
|
// ------------------------
|
|
// Misaligned Exception
|
|
// ------------------------
|
|
// we can detect a misaligned exception immediately
|
|
// the misaligned exception is passed to the functional unit via the MMU, which in case
|
|
// can augment the exception if other memory related exceptions like a page fault or access errors
|
|
always_comb begin : data_misaligned_detection
|
|
misaligned_exception = {
|
|
{CVA6Cfg.XLEN{1'b0}}, {CVA6Cfg.XLEN{1'b0}}, {CVA6Cfg.GPLEN{1'b0}}, {32{1'b0}}, 1'b0, 1'b0
|
|
};
|
|
data_misaligned = 1'b0;
|
|
|
|
if (lsu_ctrl.valid) begin
|
|
case (lsu_ctrl.operation)
|
|
// double word
|
|
LD, SD, FLD, FSD,
|
|
AMO_LRD, AMO_SCD,
|
|
AMO_SWAPD, AMO_ADDD, AMO_ANDD, AMO_ORD,
|
|
AMO_XORD, AMO_MAXD, AMO_MAXDU, AMO_MIND,
|
|
AMO_MINDU, HLV_D, HSV_D: begin
|
|
if (CVA6Cfg.IS_XLEN64 && lsu_ctrl.vaddr[2:0] != 3'b000) begin
|
|
data_misaligned = 1'b1;
|
|
end
|
|
end
|
|
// word
|
|
LW, LWU, SW, FLW, FSW,
|
|
AMO_LRW, AMO_SCW,
|
|
AMO_SWAPW, AMO_ADDW, AMO_ANDW, AMO_ORW,
|
|
AMO_XORW, AMO_MAXW, AMO_MAXWU, AMO_MINW,
|
|
AMO_MINWU, HLV_W, HLV_WU, HLVX_WU, HSV_W: begin
|
|
if (lsu_ctrl.vaddr[1:0] != 2'b00) begin
|
|
data_misaligned = 1'b1;
|
|
end
|
|
end
|
|
// half word
|
|
LH, LHU, SH, FLH, FSH, HLV_H, HLV_HU, HLVX_HU, HSV_H: begin
|
|
if (lsu_ctrl.vaddr[0] != 1'b0) begin
|
|
data_misaligned = 1'b1;
|
|
end
|
|
end
|
|
// byte -> is always aligned
|
|
default: ;
|
|
endcase
|
|
end
|
|
|
|
if (data_misaligned) begin
|
|
|
|
if (lsu_ctrl.fu == LOAD) begin
|
|
misaligned_exception.cause = riscv::LD_ADDR_MISALIGNED;
|
|
misaligned_exception.valid = 1'b1;
|
|
if (CVA6Cfg.TvalEn)
|
|
misaligned_exception.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr};
|
|
if (CVA6Cfg.RVH) begin
|
|
misaligned_exception.tval2 = '0;
|
|
misaligned_exception.tinst = lsu_ctrl.tinst;
|
|
misaligned_exception.gva = ld_st_v_i;
|
|
end
|
|
|
|
end else if (lsu_ctrl.fu == STORE) begin
|
|
misaligned_exception.cause = riscv::ST_ADDR_MISALIGNED;
|
|
misaligned_exception.valid = 1'b1;
|
|
if (CVA6Cfg.TvalEn)
|
|
misaligned_exception.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr};
|
|
if (CVA6Cfg.RVH) begin
|
|
misaligned_exception.tval2 = '0;
|
|
misaligned_exception.tinst = lsu_ctrl.tinst;
|
|
misaligned_exception.gva = ld_st_v_i;
|
|
end
|
|
end
|
|
end
|
|
|
|
if (CVA6Cfg.MmuPresent && en_ld_st_translation_i && lsu_ctrl.overflow) begin
|
|
|
|
if (lsu_ctrl.fu == LOAD) begin
|
|
misaligned_exception.cause = riscv::LD_ACCESS_FAULT;
|
|
misaligned_exception.valid = 1'b1;
|
|
if (CVA6Cfg.TvalEn)
|
|
misaligned_exception.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr};
|
|
if (CVA6Cfg.RVH) begin
|
|
misaligned_exception.tval2 = '0;
|
|
misaligned_exception.tinst = lsu_ctrl.tinst;
|
|
misaligned_exception.gva = ld_st_v_i;
|
|
end
|
|
|
|
end else if (lsu_ctrl.fu == STORE) begin
|
|
misaligned_exception.cause = riscv::ST_ACCESS_FAULT;
|
|
misaligned_exception.valid = 1'b1;
|
|
if (CVA6Cfg.TvalEn)
|
|
misaligned_exception.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr};
|
|
if (CVA6Cfg.RVH) begin
|
|
misaligned_exception.tval2 = '0;
|
|
misaligned_exception.tinst = lsu_ctrl.tinst;
|
|
misaligned_exception.gva = ld_st_v_i;
|
|
end
|
|
end
|
|
end
|
|
|
|
if (CVA6Cfg.MmuPresent && CVA6Cfg.RVH && en_ld_st_g_translation_i && !en_ld_st_translation_i && lsu_ctrl.g_overflow) begin
|
|
|
|
if (lsu_ctrl.fu == LOAD) begin
|
|
misaligned_exception.cause = riscv::LOAD_GUEST_PAGE_FAULT;
|
|
misaligned_exception.valid = 1'b1;
|
|
if (CVA6Cfg.TvalEn)
|
|
misaligned_exception.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr};
|
|
if (CVA6Cfg.RVH) begin
|
|
misaligned_exception.tval2 = '0;
|
|
misaligned_exception.tinst = lsu_ctrl.tinst;
|
|
misaligned_exception.gva = ld_st_v_i;
|
|
end
|
|
end else if (lsu_ctrl.fu == STORE) begin
|
|
misaligned_exception.cause = riscv::STORE_GUEST_PAGE_FAULT;
|
|
misaligned_exception.valid = 1'b1;
|
|
if (CVA6Cfg.TvalEn)
|
|
misaligned_exception.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr};
|
|
if (CVA6Cfg.RVH) begin
|
|
misaligned_exception.tval2 = '0;
|
|
misaligned_exception.tinst = lsu_ctrl.tinst;
|
|
misaligned_exception.gva = ld_st_v_i;
|
|
end
|
|
end
|
|
end
|
|
end
|
|
|
|
// ------------------
|
|
// LSU Control
|
|
// ------------------
|
|
// new data arrives here
|
|
lsu_ctrl_t lsu_req_i;
|
|
|
|
assign lsu_req_i = {
|
|
lsu_valid_i,
|
|
vaddr_i,
|
|
tinst_i,
|
|
hs_ld_st_inst,
|
|
hlvx_inst,
|
|
overflow,
|
|
g_overflow,
|
|
fu_data_i.operand_b,
|
|
be_i,
|
|
fu_data_i.fu,
|
|
fu_data_i.operation,
|
|
fu_data_i.trans_id
|
|
};
|
|
|
|
lsu_bypass #(
|
|
.CVA6Cfg(CVA6Cfg),
|
|
.lsu_ctrl_t(lsu_ctrl_t)
|
|
) lsu_bypass_i (
|
|
.lsu_req_i (lsu_req_i),
|
|
.lsu_req_valid_i(lsu_valid_i),
|
|
.pop_ld_i (pop_ld),
|
|
.pop_st_i (pop_st),
|
|
|
|
.lsu_ctrl_o(lsu_ctrl),
|
|
.ready_o (lsu_ready_o),
|
|
.*
|
|
);
|
|
|
|
assign rvfi_lsu_ctrl_o = lsu_ctrl;
|
|
|
|
endmodule
|
|
|