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6d08ed1389
Fix fence.i synchronization issue with HPDCache write-back Data Add [halt_frontend_o] signal to stall instruction fetch during fence.i Introduce [fence_i_active] state to track ICache+DCache flush progress Gate ICache requests and NPC updates when fence.i is active Resolves stale instruction fetch in self-modifying code scenarios (riscv-tests/rv32ui/fence_i) Enables Linux boot with HPDCache write-back data by ensuring ICache/DCache coherency Note: This was not seen with [std_dcache] in standard [fence_i] tests, since it normally finishes write‑back before the ICache flush completes. However, for large self‑modifying code regions, the write‑back can lag behind the ICache flush, leading to stale instruction fetches even with [std_dcache]. Problem: When executing self-modifying code or booting Linux with a write-back D$, fence.i flushes the ICache but allows the frontend to fetch new instructions before the DCache flush completes. This causes the core to execute stale instructions from the ICache that were modified in the DCache (Dirty data may not be written back because the DCache is still flushing). Root Cause: The frontend resumes fetching immediately after ICache flush, even if the DCache is still flushing. NPC (Next PC) continues advancing after ICache flush, leading to incorrect instruction fetch. Solution: Introduce halt_frontend_o signal to freeze frontend during fence.i. Add fence_i_active state in controller to track combined ICache+DCache flush. Gate ICache requests (icache_dreq_o.req) and NPC updates (if_ready) during fence_i_active. |
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| .. | ||
| bht.sv | ||
| bht2lvl.sv | ||
| btb.sv | ||
| frontend.sv | ||
| instr_queue.sv | ||
| instr_scan.sv | ||
| ras.sv | ||