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André Sintzoff 9fca53c342 [SPIKE] sim.cc: do not yield load reservation on single core 
to have same behaviour on spike and on RTL with one core,
do not yield load reservation at the end of each block of
INTERLEAVE steps


Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
2023-08-04 16:55:28 +02:00
..
patches/riscv/riscv-isa-sim [SPIKE] sim.cc: do not yield load reservation on single core 2023-08-04 16:55:28 +02:00
riscv/riscv-isa-sim [SPIKE] sim.cc: do not yield load reservation on single core 2023-08-04 16:55:28 +02:00
riscv_riscv-isa-sim.lock.hjson [Spike] Result of running 'vendor.py --update' w/updated patch set. 2023-05-29 14:57:43 +02:00
riscv_riscv-isa-sim.vendor.hjson [Spike] Update upstream vendor hash to be retrieved. 2023-05-29 14:57:42 +02:00