mirror of
https://github.com/openhwgroup/cva6.git
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aae9b2eb66
This PR adds a new two-level BHT predictor with private history. The new BPType parameters allow choosing between the original BHT and the new one. Co-authored-by: Gianmarco Ottavi <ottavig91@gmail.com>
465 lines
16 KiB
Systemverilog
465 lines
16 KiB
Systemverilog
// Copyright 2023 Thales DIS France SAS
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//
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// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
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// You may obtain a copy of the License at https://solderpad.org/licenses/
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//
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// Original Author: Jean-Roch COULON - Thales
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package config_pkg;
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// ---------------
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// Global Config
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// ---------------
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localparam int unsigned ILEN = 32;
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localparam int unsigned NRET = 1;
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/// The NoC type is a top-level parameter, hence we need a bit more
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/// information on what protocol those type parameters are supporting.
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/// Currently two values are supported"
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typedef enum {
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/// The "classic" AXI4 protocol.
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NOC_TYPE_AXI4_ATOP,
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/// In the OpenPiton setting the WT cache is connected to the L15.
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NOC_TYPE_L15_BIG_ENDIAN,
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NOC_TYPE_L15_LITTLE_ENDIAN
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} noc_type_e;
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/// Cache type parameter
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typedef enum logic [2:0] {
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WB = 0,
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WT = 1,
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HPDCACHE_WT = 2,
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HPDCACHE_WB = 3,
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HPDCACHE_WT_WB = 4
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} cache_type_t;
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/// Branch predictor parameter
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typedef enum logic {
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BHT = 0, // Bimodal predictor
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PH_BHT = 1 // Private History Bimodal predictor
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} bp_type_t;
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/// Data and Address length
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typedef enum logic [3:0] {
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ModeOff = 0,
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ModeSv32 = 1,
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ModeSv39 = 8,
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ModeSv48 = 9,
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ModeSv57 = 10,
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ModeSv64 = 11
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} vm_mode_t;
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/// Coprocessor type parameter
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typedef enum {
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COPRO_NONE,
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COPRO_EXAMPLE
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} copro_type_t;
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localparam NrMaxRules = 16;
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typedef struct packed {
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// General Purpose Register Size (in bits)
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int unsigned XLEN;
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// Virtual address Size (in bits)
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int unsigned VLEN;
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// Atomic RISC-V extension
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bit RVA;
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// Bit manipulation RISC-V extension
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bit RVB;
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// Scalar Cryptography RISC-V entension
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bit ZKN;
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// Vector RISC-V extension
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bit RVV;
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// Compress RISC-V extension
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bit RVC;
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// Hypervisor RISC-V extension
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bit RVH;
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// Zcb RISC-V extension
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bit RVZCB;
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// Zcmp RISC-V extension
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bit RVZCMP;
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// Zcmt RISC-V extension
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bit RVZCMT;
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// Zicond RISC-V extension
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bit RVZiCond;
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// Zicntr RISC-V extension
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bit RVZicntr;
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// Zihpm RISC-V extension
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bit RVZihpm;
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// Floating Point
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bit RVF;
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// Floating Point
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bit RVD;
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// Non standard 16bits Floating Point extension
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bit XF16;
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// Non standard 16bits Floating Point Alt extension
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bit XF16ALT;
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// Non standard 8bits Floating Point extension
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bit XF8;
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// Non standard Vector Floating Point extension
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bit XFVec;
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// Perf counters
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bit PerfCounterEn;
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// MMU
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bit MmuPresent;
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// Supervisor mode
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bit RVS;
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// User mode
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bit RVU;
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// Software interrupts are enabled
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bit SoftwareInterruptEn;
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// Debug support
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bit DebugEn;
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// Base address of the debug module
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logic [63:0] DmBaseAddress;
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// Address to jump when halt request
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logic [63:0] HaltAddress;
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// Address to jump when exception
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logic [63:0] ExceptionAddress;
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// Tval Support Enable
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bit TvalEn;
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// MTVEC CSR supports only direct mode
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bit DirectVecOnly;
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// PMP entries number
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int unsigned NrPMPEntries;
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// PMP CSR configuration reset values
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logic [63:0][63:0] PMPCfgRstVal;
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// PMP CSR address reset values
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logic [63:0][63:0] PMPAddrRstVal;
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// PMP CSR read-only bits
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bit [63:0] PMPEntryReadOnly;
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// PMP NA4 and NAPOT mode enable
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bit PMPNapotEn;
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// PMA non idempotent rules number
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int unsigned NrNonIdempotentRules;
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// PMA NonIdempotent region base address
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logic [NrMaxRules-1:0][63:0] NonIdempotentAddrBase;
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// PMA NonIdempotent region length
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logic [NrMaxRules-1:0][63:0] NonIdempotentLength;
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// PMA regions with execute rules number
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int unsigned NrExecuteRegionRules;
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// PMA Execute region base address
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logic [NrMaxRules-1:0][63:0] ExecuteRegionAddrBase;
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// PMA Execute region address base
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logic [NrMaxRules-1:0][63:0] ExecuteRegionLength;
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// PMA regions with cache rules number
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int unsigned NrCachedRegionRules;
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// PMA cache region base address
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logic [NrMaxRules-1:0][63:0] CachedRegionAddrBase;
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// PMA cache region rules
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logic [NrMaxRules-1:0][63:0] CachedRegionLength;
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// CV-X-IF coprocessor interface enable
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bit CvxifEn;
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// Coprocessor type
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copro_type_t CoproType;
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// NOC bus type
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noc_type_e NOCType;
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// AXI address width
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int unsigned AxiAddrWidth;
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// AXI data width
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int unsigned AxiDataWidth;
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// AXI ID width
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int unsigned AxiIdWidth;
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// AXI User width
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int unsigned AxiUserWidth;
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// AXI burst in write
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bit AxiBurstWriteEn;
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// TODO
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int unsigned MemTidWidth;
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// Instruction cache size (in bytes)
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int unsigned IcacheByteSize;
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// Instruction cache associativity (number of ways)
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int unsigned IcacheSetAssoc;
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// Instruction cache line width
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int unsigned IcacheLineWidth;
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// Cache Type
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cache_type_t DCacheType;
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// Data cache ID
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int unsigned DcacheIdWidth;
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// Data cache size (in bytes)
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int unsigned DcacheByteSize;
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// Data cache associativity (number of ways)
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int unsigned DcacheSetAssoc;
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// Data cache line width
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int unsigned DcacheLineWidth;
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// Data cache flush on fence
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bit DcacheFlushOnFence;
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// Data cache invalidate on flush
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bit DcacheInvalidateOnFlush;
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// User field on data bus enable
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int unsigned DataUserEn;
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// Write-through data cache write buffer depth
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int unsigned WtDcacheWbufDepth;
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// User field on fetch bus enable
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int unsigned FetchUserEn;
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// Width of fetch user field
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int unsigned FetchUserWidth;
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// Is FPGA optimization of CV32A6 for Xilinx and Altera
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bit FpgaEn;
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// Is FPGA optimization for Altera FPGA
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bit FpgaAlteraEn;
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// Is Techno Cut instanciated
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bit TechnoCut;
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// Enable superscalar* with 2 issue ports and 2 commit ports.
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bit SuperscalarEn;
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// Number of commit ports. Forced to 2 if SuperscalarEn.
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int unsigned NrCommitPorts;
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// Load cycle latency number
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int unsigned NrLoadPipeRegs;
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// Store cycle latency number
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int unsigned NrStorePipeRegs;
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// Scoreboard length
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int unsigned NrScoreboardEntries;
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// Load buffer entry buffer
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int unsigned NrLoadBufEntries;
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// Maximum number of outstanding stores
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int unsigned MaxOutstandingStores;
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// Return address stack depth
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int unsigned RASDepth;
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// Branch target buffer entries
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int unsigned BTBEntries;
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// Branch predictor type
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bp_type_t BPType;
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// Branch history entries
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int unsigned BHTEntries;
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// Branch history bits
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int unsigned BHTHist;
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// MMU instruction TLB entries
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int unsigned InstrTlbEntries;
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// MMU data TLB entries
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int unsigned DataTlbEntries;
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// MMU option to use shared TLB
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bit unsigned UseSharedTlb;
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// MMU depth of shared TLB
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int unsigned SharedTlbDepth;
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} cva6_user_cfg_t;
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typedef struct packed {
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int unsigned XLEN;
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int unsigned VLEN;
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int unsigned PLEN;
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int unsigned GPLEN;
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bit IS_XLEN32;
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bit IS_XLEN64;
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int unsigned XLEN_ALIGN_BYTES;
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int unsigned ASID_WIDTH;
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int unsigned VMID_WIDTH;
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bit FpgaEn;
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bit FpgaAlteraEn;
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bit TechnoCut;
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bit SuperscalarEn;
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int unsigned NrCommitPorts;
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int unsigned NrIssuePorts;
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bit SpeculativeSb;
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int unsigned NrLoadPipeRegs;
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int unsigned NrStorePipeRegs;
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/// AXI parameters.
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int unsigned AxiAddrWidth;
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int unsigned AxiDataWidth;
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int unsigned AxiIdWidth;
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int unsigned AxiUserWidth;
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int unsigned MEM_TID_WIDTH;
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int unsigned NrLoadBufEntries;
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bit RVF;
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bit RVD;
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bit XF16;
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bit XF16ALT;
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bit XF8;
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bit RVA;
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bit RVB;
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bit ZKN;
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bit RVV;
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bit RVC;
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bit RVH;
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bit RVZCB;
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bit RVZCMP;
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bit RVZCMT;
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bit XFVec;
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bit CvxifEn;
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copro_type_t CoproType;
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bit RVZiCond;
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bit RVZicntr;
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bit RVZihpm;
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int unsigned NR_SB_ENTRIES;
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int unsigned TRANS_ID_BITS;
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bit FpPresent;
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bit NSX;
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int unsigned FLen;
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bit RVFVec;
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bit XF16Vec;
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bit XF16ALTVec;
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bit XF8Vec;
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int unsigned NrRgprPorts;
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int unsigned NrWbPorts;
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bit EnableAccelerator;
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bit PerfCounterEn;
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bit MmuPresent;
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bit RVS; //Supervisor mode
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bit RVU; //User mode
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bit SoftwareInterruptEn;
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logic [63:0] HaltAddress;
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logic [63:0] ExceptionAddress;
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int unsigned RASDepth;
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int unsigned BTBEntries;
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bp_type_t BPType;
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int unsigned BHTEntries;
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int unsigned BHTHist;
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int unsigned InstrTlbEntries;
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int unsigned DataTlbEntries;
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bit unsigned UseSharedTlb;
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int unsigned SharedTlbDepth;
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int unsigned VpnLen;
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int unsigned PtLevels;
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logic [63:0] DmBaseAddress;
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bit TvalEn;
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bit DirectVecOnly;
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int unsigned NrPMPEntries;
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logic [63:0][63:0] PMPCfgRstVal;
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logic [63:0][63:0] PMPAddrRstVal;
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bit [63:0] PMPEntryReadOnly;
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bit PMPNapotEn;
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noc_type_e NOCType;
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int unsigned NrNonIdempotentRules;
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logic [NrMaxRules-1:0][63:0] NonIdempotentAddrBase;
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logic [NrMaxRules-1:0][63:0] NonIdempotentLength;
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int unsigned NrExecuteRegionRules;
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logic [NrMaxRules-1:0][63:0] ExecuteRegionAddrBase;
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logic [NrMaxRules-1:0][63:0] ExecuteRegionLength;
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int unsigned NrCachedRegionRules;
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logic [NrMaxRules-1:0][63:0] CachedRegionAddrBase;
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logic [NrMaxRules-1:0][63:0] CachedRegionLength;
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int unsigned MaxOutstandingStores;
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bit DebugEn;
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bit NonIdemPotenceEn; // Currently only used by V extension (Ara)
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bit AxiBurstWriteEn;
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int unsigned ICACHE_SET_ASSOC;
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int unsigned ICACHE_SET_ASSOC_WIDTH;
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int unsigned ICACHE_INDEX_WIDTH;
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int unsigned ICACHE_TAG_WIDTH;
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int unsigned ICACHE_LINE_WIDTH;
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int unsigned ICACHE_USER_LINE_WIDTH;
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cache_type_t DCacheType;
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int unsigned DcacheIdWidth;
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int unsigned DCACHE_SET_ASSOC;
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int unsigned DCACHE_SET_ASSOC_WIDTH;
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int unsigned DCACHE_INDEX_WIDTH;
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int unsigned DCACHE_TAG_WIDTH;
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int unsigned DCACHE_LINE_WIDTH;
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int unsigned DCACHE_USER_LINE_WIDTH;
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int unsigned DCACHE_USER_WIDTH;
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int unsigned DCACHE_OFFSET_WIDTH;
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int unsigned DCACHE_NUM_WORDS;
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int unsigned DCACHE_MAX_TX;
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bit DcacheFlushOnFence;
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bit DcacheInvalidateOnFlush;
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int unsigned DATA_USER_EN;
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int unsigned WtDcacheWbufDepth;
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int unsigned FETCH_USER_WIDTH;
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int unsigned FETCH_USER_EN;
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bit AXI_USER_EN;
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int unsigned FETCH_WIDTH;
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int unsigned FETCH_ALIGN_BITS;
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int unsigned INSTR_PER_FETCH;
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int unsigned LOG2_INSTR_PER_FETCH;
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int unsigned ModeW;
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int unsigned ASIDW;
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int unsigned VMIDW;
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int unsigned PPNW;
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int unsigned GPPNW;
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vm_mode_t MODE_SV;
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int unsigned SV;
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int unsigned SVX;
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int unsigned X_NUM_RS;
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int unsigned X_ID_WIDTH;
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int unsigned X_RFR_WIDTH;
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int unsigned X_RFW_WIDTH;
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int unsigned X_NUM_HARTS;
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int unsigned X_HARTID_WIDTH;
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int unsigned X_DUALREAD;
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int unsigned X_DUALWRITE;
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int unsigned X_ISSUE_REGISTER_SPLIT;
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} cva6_cfg_t;
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/// Empty configuration to sanity check proper parameter passing. Whenever
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/// you develop a module that resides within the core, assign this constant.
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localparam cva6_cfg_t cva6_cfg_empty = cva6_cfg_t'(0);
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/// Utility function being called to check parameters. Not all values make
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/// sense for all parameters, here is the place to sanity check them.
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function automatic void check_cfg(cva6_cfg_t Cfg);
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// pragma translate_off
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assert (Cfg.RASDepth > 0);
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assert (Cfg.BTBEntries == 0 || (2 ** $clog2(Cfg.BTBEntries) == Cfg.BTBEntries));
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assert (Cfg.BHTEntries == 0 || (2 ** $clog2(Cfg.BHTEntries) == Cfg.BHTEntries));
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assert (Cfg.NrNonIdempotentRules <= NrMaxRules);
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assert (Cfg.NrExecuteRegionRules <= NrMaxRules);
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assert (Cfg.NrCachedRegionRules <= NrMaxRules);
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assert (Cfg.NrPMPEntries <= 64);
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assert (!(Cfg.SuperscalarEn && Cfg.RVF));
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assert (Cfg.FETCH_WIDTH == 32 || Cfg.FETCH_WIDTH == 64)
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else $fatal(1, "[frontend] fetch width != not supported");
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// Support for disabling MIP.MSIP and MIE.MSIE in Hypervisor and Supervisor mode is not supported
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// Software Interrupt can be disabled when there is only M machine mode in CVA6.
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assert (!(Cfg.RVS && !Cfg.SoftwareInterruptEn));
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assert (!(Cfg.RVH && !Cfg.SoftwareInterruptEn));
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assert (!(Cfg.RVZCMT && ~Cfg.MmuPresent));
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// pragma translate_on
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endfunction
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function automatic logic range_check(logic [63:0] base, logic [63:0] len, logic [63:0] address);
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// if len is a power of two, and base is properly aligned, this check could be simplified
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// Extend base by one bit to prevent an overflow.
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return (address >= base) && (({1'b0, address}) < (65'(base) + len));
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endfunction : range_check
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function automatic logic is_inside_nonidempotent_regions(cva6_cfg_t Cfg, logic [63:0] address);
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logic [NrMaxRules-1:0] pass;
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pass = '0;
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for (int unsigned k = 0; k < Cfg.NrNonIdempotentRules; k++) begin
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pass[k] = range_check(Cfg.NonIdempotentAddrBase[k], Cfg.NonIdempotentLength[k], address);
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end
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return |pass;
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endfunction : is_inside_nonidempotent_regions
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function automatic logic is_inside_execute_regions(cva6_cfg_t Cfg, logic [63:0] address);
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// if we don't specify any region we assume everything is accessible
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logic [NrMaxRules-1:0] pass;
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if (Cfg.NrExecuteRegionRules != 0) begin
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pass = '0;
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for (int unsigned k = 0; k < Cfg.NrExecuteRegionRules; k++) begin
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pass[k] = range_check(Cfg.ExecuteRegionAddrBase[k], Cfg.ExecuteRegionLength[k], address);
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end
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return |pass;
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end else begin
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return 1;
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end
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endfunction : is_inside_execute_regions
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function automatic logic is_inside_cacheable_regions(cva6_cfg_t Cfg, logic [63:0] address);
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automatic logic [NrMaxRules-1:0] pass;
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pass = '0;
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for (int unsigned k = 0; k < Cfg.NrCachedRegionRules; k++) begin
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pass[k] = range_check(Cfg.CachedRegionAddrBase[k], Cfg.CachedRegionLength[k], address);
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end
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return |pass;
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endfunction : is_inside_cacheable_regions
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endpackage
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