mirror of
https://github.com/openhwgroup/cva6.git
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aae9b2eb66
This PR adds a new two-level BHT predictor with private history. The new BPType parameters allow choosing between the original BHT and the new one. Co-authored-by: Gianmarco Ottavi <ottavig91@gmail.com>
111 lines
3.6 KiB
Systemverilog
111 lines
3.6 KiB
Systemverilog
// Copyright 2022 Thales DIS design services SAS
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//
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// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
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// You may obtain a copy of the License at https://solderpad.org/licenses/
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//
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// Original Author: Jean-Roch COULON - Thales
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package cva6_config_pkg;
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localparam CVA6ConfigXlen = 32;
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localparam CVA6ConfigRvfiTrace = 1;
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localparam CVA6ConfigAxiIdWidth = 4; // axi_pkg.sv
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localparam CVA6ConfigAxiAddrWidth = 64; // axi_pkg.sv
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localparam CVA6ConfigAxiDataWidth = 64; // axi_pkg.sv
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localparam CVA6ConfigDataUserWidth = 32; // axi_pkg.sv
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localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
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XLEN: unsigned'(CVA6ConfigXlen),
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VLEN: unsigned'(32),
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FpgaEn: bit'(0),
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FpgaAlteraEn: bit'(0),
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TechnoCut: bit'(1),
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SuperscalarEn: bit'(0),
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NrCommitPorts: unsigned'(1),
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AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth),
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AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth),
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AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth),
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AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth),
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MemTidWidth: unsigned'(CVA6ConfigAxiIdWidth),
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NrLoadBufEntries: unsigned'(2),
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RVF: bit'(0),
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RVD: bit'(0),
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XF16: bit'(0),
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XF16ALT: bit'(0),
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XF8: bit'(0),
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RVA: bit'(0),
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RVB: bit'(1),
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ZKN: bit'(0),
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RVV: bit'(0),
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RVC: bit'(1),
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RVH: bit'(0),
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RVZCMT: bit'(0),
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RVZCB: bit'(1),
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RVZCMP: bit'(0),
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XFVec: bit'(0),
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CvxifEn: bit'(1),
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CoproType: config_pkg::COPRO_EXAMPLE,
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RVZiCond: bit'(0),
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RVZicntr: bit'(0),
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RVZihpm: bit'(0),
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NrScoreboardEntries: unsigned'(4),
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PerfCounterEn: bit'(0),
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MmuPresent: bit'(0),
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RVS: bit'(0),
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RVU: bit'(0),
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SoftwareInterruptEn: bit'(0),
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HaltAddress: 64'h800,
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ExceptionAddress: 64'h808,
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RASDepth: unsigned'(2),
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BTBEntries: unsigned'(0),
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BPType: config_pkg::BHT,
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BHTEntries: unsigned'(32),
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BHTHist: unsigned'(3),
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DmBaseAddress: 64'h0,
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TvalEn: bit'(0),
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DirectVecOnly: bit'(1),
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NrPMPEntries: unsigned'(8),
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PMPCfgRstVal: {64{64'h0}},
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PMPAddrRstVal: {64{64'h0}},
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PMPEntryReadOnly: 64'd0,
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PMPNapotEn: bit'(0),
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NOCType: config_pkg::NOC_TYPE_AXI4_ATOP,
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NrNonIdempotentRules: unsigned'(0),
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NonIdempotentAddrBase: 1024'({64'b0, 64'b0}),
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NonIdempotentLength: 1024'({64'b0, 64'b0}),
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NrExecuteRegionRules: unsigned'(0),
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ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}),
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ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}),
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NrCachedRegionRules: unsigned'(1),
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CachedRegionAddrBase: 1024'({64'h8000_0000}),
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CachedRegionLength: 1024'({64'h40000000}),
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MaxOutstandingStores: unsigned'(7),
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DebugEn: bit'(0),
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AxiBurstWriteEn: bit'(0),
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IcacheByteSize: unsigned'(2048),
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IcacheSetAssoc: unsigned'(2),
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IcacheLineWidth: unsigned'(128),
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DCacheType: config_pkg::HPDCACHE_WT,
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DcacheByteSize: unsigned'(2028),
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DcacheSetAssoc: unsigned'(2),
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DcacheLineWidth: unsigned'(128),
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DcacheFlushOnFence: bit'(0),
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DcacheInvalidateOnFlush: bit'(0),
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DataUserEn: unsigned'(1),
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WtDcacheWbufDepth: int'(8),
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FetchUserWidth: unsigned'(32),
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FetchUserEn: unsigned'(1),
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InstrTlbEntries: int'(2),
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DataTlbEntries: int'(2),
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UseSharedTlb: bit'(1),
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SharedTlbDepth: int'(64),
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NrLoadPipeRegs: int'(0),
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NrStorePipeRegs: int'(0),
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DcacheIdWidth: int'(1)
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};
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endpackage
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