cva6/fpga
David Schrammel afea42d650
Copy actual partition size instead of hardcoded 16MB (#627)
Signed-off-by: David Schrammel <david.schrammel@iaik.tugraz.at>
2021-03-04 09:48:04 +01:00
..
constraints fpga: Add VC707 compatibility (#335) 2019-10-11 13:41:41 +02:00
scripts fpga: Fix IP synthesis for Vivado 2020.2 (#604) 2021-02-08 17:51:01 +01:00
src Copy actual partition size instead of hardcoded 16MB (#627) 2021-03-04 09:48:04 +01:00
xilinx fpga: Fix IP synthesis for Vivado 2020.2 (#604) 2021-02-08 17:51:01 +01:00
.gitignore Put batch flow in place (incl small flow fixes) 2018-11-19 19:24:31 +01:00
ariane-multi-hart.cfg openocd: Add multi-hart config 2019-06-04 10:36:17 +02:00
ariane.cfg ariane.cfg: catch unavailable address translation option 2019-12-03 13:31:08 +01:00
ariane_pmod.cfg Rerouting RISC-V DTM JTAG from PMOD header to 2nd channel of FTDI chip. 2019-01-30 11:36:34 +01:00
ariane_pmod_tiny.cfg Rerouting RISC-V DTM JTAG from PMOD header to 2nd channel of FTDI chip. 2019-01-30 11:36:34 +01:00
Makefile fpga: Fix IP synthesis for Vivado 2020.2 (#604) 2021-02-08 17:51:01 +01:00
sourceme.sh fpga: Add VC707 compatibility (#335) 2019-10-11 13:41:41 +02:00