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dc103cd49f
* Clean-up README.md and top-level directory This removes the duplicate `scripts` and `util` directories. Furthermore the README is condensed by collapsing the citation and adding the CITATION file to the repository. Signed-off-by: Florian Zaruba <florian@openhwgroup.org> * Re-name icache req/rsp structs The structs used to communicate with the icache have contained the direction, which makes no sense for structs since they inherently don't have any direction. Signed-off-by: Florian Zaruba <florian@openhwgroup.org> --------- Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
500 lines
20 KiB
Systemverilog
500 lines
20 KiB
Systemverilog
// Copyright 2018 ETH Zurich and University of Bologna.
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// Copyright and related rights are licensed under the Solderpad Hardware
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// License, Version 0.51 (the "License"); you may not use this file except in
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// compliance with the License. You may obtain a copy of the License at
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// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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// or agreed to in writing, software, hardware and materials distributed under
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// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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// CONDITIONS OF ANY KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations under the License.
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//
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// Author: Florian Zaruba, ETH Zurich
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// Date: 19.04.2017
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// Description: Load Store Unit, handles address calculation and memory interface signals
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module load_store_unit import ariane_pkg::*; #(
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parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
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parameter int unsigned ASID_WIDTH = 1,
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parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig
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)(
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input logic clk_i,
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input logic rst_ni,
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input logic flush_i,
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input logic stall_st_pending_i,
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output logic no_st_pending_o,
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input logic amo_valid_commit_i,
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input fu_data_t fu_data_i,
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output logic lsu_ready_o, // FU is ready e.g. not busy
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input logic lsu_valid_i, // Input is valid
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output logic [TRANS_ID_BITS-1:0] load_trans_id_o, // ID of scoreboard entry at which to write back
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output riscv::xlen_t load_result_o,
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output logic load_valid_o,
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output exception_t load_exception_o, // to WB, signal exception status LD exception
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output logic [TRANS_ID_BITS-1:0] store_trans_id_o, // ID of scoreboard entry at which to write back
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output riscv::xlen_t store_result_o,
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output logic store_valid_o,
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output exception_t store_exception_o, // to WB, signal exception status ST exception
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input logic commit_i, // commit the pending store
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output logic commit_ready_o, // commit queue is ready to accept another commit request
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input logic [TRANS_ID_BITS-1:0] commit_tran_id_i,
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input logic enable_translation_i, // enable virtual memory translation
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input logic en_ld_st_translation_i, // enable virtual memory translation for load/stores
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// icache translation requests
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input icache_arsp_t icache_areq_i,
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output icache_areq_t icache_areq_o,
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input riscv::priv_lvl_t priv_lvl_i, // From CSR register file
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input riscv::priv_lvl_t ld_st_priv_lvl_i, // From CSR register file
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input logic sum_i, // From CSR register file
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input logic mxr_i, // From CSR register file
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input logic [riscv::PPNW-1:0] satp_ppn_i, // From CSR register file
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input logic [ASID_WIDTH-1:0] asid_i, // From CSR register file
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input logic [ASID_WIDTH-1:0] asid_to_be_flushed_i,
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input logic [riscv::VLEN-1:0] vaddr_to_be_flushed_i,
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input logic flush_tlb_i,
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// Performance counters
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output logic itlb_miss_o,
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output logic dtlb_miss_o,
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// interface to dcache
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input dcache_req_o_t [2:0] dcache_req_ports_i,
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output dcache_req_i_t [2:0] dcache_req_ports_o,
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input logic dcache_wbuffer_empty_i,
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input logic dcache_wbuffer_not_ni_i,
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// AMO interface
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output amo_req_t amo_req_o,
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input amo_resp_t amo_resp_i,
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// PMP
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input riscv::pmpcfg_t [15:0] pmpcfg_i,
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input logic [15:0][riscv::PLEN-3:0] pmpaddr_i,
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//RVFI
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output [riscv::VLEN-1:0] lsu_addr_o,
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output [riscv::PLEN-1:0] mem_paddr_o,
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output [(riscv::XLEN/8)-1:0] lsu_rmask_o,
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output [(riscv::XLEN/8)-1:0] lsu_wmask_o,
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output [ariane_pkg::TRANS_ID_BITS-1:0] lsu_addr_trans_id_o
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);
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// data is misaligned
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logic data_misaligned;
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// --------------------------------------
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// 1st register stage - (stall registers)
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// --------------------------------------
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// those are the signals which are always correct
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// e.g.: they keep the value in the stall case
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lsu_ctrl_t lsu_ctrl;
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logic pop_st;
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logic pop_ld;
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// ------------------------------
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// Address Generation Unit (AGU)
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// ------------------------------
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// virtual address as calculated by the AGU in the first cycle
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logic [riscv::VLEN-1:0] vaddr_i;
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riscv::xlen_t vaddr_xlen;
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logic overflow;
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logic [(riscv::XLEN/8)-1:0] be_i;
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assign vaddr_xlen = $unsigned($signed(fu_data_i.imm) + $signed(fu_data_i.operand_a));
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assign vaddr_i = vaddr_xlen[riscv::VLEN-1:0];
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// we work with SV39 or SV32, so if VM is enabled, check that all bits [XLEN-1:38] or [XLEN-1:31] are equal
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assign overflow = !((&vaddr_xlen[riscv::XLEN-1:riscv::SV-1]) == 1'b1 || (|vaddr_xlen[riscv::XLEN-1:riscv::SV-1]) == 1'b0);
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logic st_valid_i;
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logic ld_valid_i;
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logic ld_translation_req;
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logic st_translation_req;
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logic [riscv::VLEN-1:0] ld_vaddr;
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logic [riscv::VLEN-1:0] st_vaddr;
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logic translation_req;
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logic translation_valid;
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logic [riscv::VLEN-1:0] mmu_vaddr;
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logic [riscv::PLEN-1:0] mmu_paddr, mmu_vaddr_plen, fetch_vaddr_plen;
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exception_t mmu_exception;
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logic dtlb_hit;
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logic [riscv::PPNW-1:0] dtlb_ppn;
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logic ld_valid;
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logic [TRANS_ID_BITS-1:0] ld_trans_id;
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riscv::xlen_t ld_result;
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logic st_valid;
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logic [TRANS_ID_BITS-1:0] st_trans_id;
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riscv::xlen_t st_result;
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logic [11:0] page_offset;
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logic page_offset_matches;
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exception_t misaligned_exception;
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exception_t ld_ex;
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exception_t st_ex;
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// -------------------
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// MMU e.g.: TLBs/PTW
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// -------------------
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if (MMU_PRESENT && (riscv::XLEN == 64)) begin : gen_mmu_sv39
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mmu #(
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.CVA6Cfg ( CVA6Cfg ),
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.INSTR_TLB_ENTRIES ( ariane_pkg::INSTR_TLB_ENTRIES ),
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.DATA_TLB_ENTRIES ( ariane_pkg::DATA_TLB_ENTRIES ),
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.ASID_WIDTH ( ASID_WIDTH ),
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.ArianeCfg ( ArianeCfg )
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) i_cva6_mmu (
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// misaligned bypass
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.misaligned_ex_i ( misaligned_exception ),
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.lsu_is_store_i ( st_translation_req ),
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.lsu_req_i ( translation_req ),
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.lsu_vaddr_i ( mmu_vaddr ),
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.lsu_valid_o ( translation_valid ),
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.lsu_paddr_o ( mmu_paddr ),
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.lsu_exception_o ( mmu_exception ),
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.lsu_dtlb_hit_o ( dtlb_hit ), // send in the same cycle as the request
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.lsu_dtlb_ppn_o ( dtlb_ppn ), // send in the same cycle as the request
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// connecting PTW to D$ IF
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.req_port_i ( dcache_req_ports_i [0] ),
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.req_port_o ( dcache_req_ports_o [0] ),
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// icache address translation requests
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.icache_areq_i ( icache_areq_i ),
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.asid_to_be_flushed_i,
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.vaddr_to_be_flushed_i,
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.icache_areq_o ( icache_areq_o ),
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.pmpcfg_i,
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.pmpaddr_i,
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.*
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);
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end else if (MMU_PRESENT && (riscv::XLEN == 32)) begin : gen_mmu_sv32
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cva6_mmu_sv32 #(
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.CVA6Cfg ( CVA6Cfg ),
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.INSTR_TLB_ENTRIES ( ariane_pkg::INSTR_TLB_ENTRIES ),
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.DATA_TLB_ENTRIES ( ariane_pkg::DATA_TLB_ENTRIES ),
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.ASID_WIDTH ( ASID_WIDTH ),
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.ArianeCfg ( ArianeCfg )
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) i_cva6_mmu (
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// misaligned bypass
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.misaligned_ex_i ( misaligned_exception ),
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.lsu_is_store_i ( st_translation_req ),
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.lsu_req_i ( translation_req ),
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.lsu_vaddr_i ( mmu_vaddr ),
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.lsu_valid_o ( translation_valid ),
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.lsu_paddr_o ( mmu_paddr ),
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.lsu_exception_o ( mmu_exception ),
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.lsu_dtlb_hit_o ( dtlb_hit ), // send in the same cycle as the request
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.lsu_dtlb_ppn_o ( dtlb_ppn ), // send in the same cycle as the request
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// connecting PTW to D$ IF
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.req_port_i ( dcache_req_ports_i [0] ),
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.req_port_o ( dcache_req_ports_o [0] ),
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// icache address translation requests
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.icache_areq_i ( icache_areq_i ),
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.asid_to_be_flushed_i,
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.vaddr_to_be_flushed_i,
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.icache_areq_o ( icache_areq_o ),
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.pmpcfg_i,
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.pmpaddr_i,
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.*
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);
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end else begin : gen_no_mmu
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if (riscv::VLEN > riscv::PLEN) begin
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assign mmu_vaddr_plen = mmu_vaddr[riscv::PLEN-1:0];
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assign fetch_vaddr_plen = icache_areq_i.fetch_vaddr[riscv::PLEN-1:0];
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end else begin
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assign mmu_vaddr_plen = {{{riscv::PLEN-riscv::VLEN}{1'b0}}, mmu_vaddr};
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assign fetch_vaddr_plen = {{{riscv::PLEN-riscv::VLEN}{1'b0}}, icache_areq_i.fetch_vaddr};
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end
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assign icache_areq_o.fetch_valid = icache_areq_i.fetch_req;
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assign icache_areq_o.fetch_paddr = fetch_vaddr_plen;
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assign icache_areq_o.fetch_exception = '0;
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assign dcache_req_ports_o[0].address_index = '0;
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assign dcache_req_ports_o[0].address_tag = '0;
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assign dcache_req_ports_o[0].data_wdata = '0;
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assign dcache_req_ports_o[0].data_req = 1'b0;
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assign dcache_req_ports_o[0].data_be = '1;
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assign dcache_req_ports_o[0].data_size = 2'b11;
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assign dcache_req_ports_o[0].data_we = 1'b0;
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assign dcache_req_ports_o[0].kill_req = '0;
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assign dcache_req_ports_o[0].tag_valid = 1'b0;
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assign itlb_miss_o = 1'b0;
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assign dtlb_miss_o = 1'b0;
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assign dtlb_ppn = mmu_vaddr_plen[riscv::PLEN-1:12];
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assign dtlb_hit = 1'b1;
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assign mmu_exception = '0;
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (~rst_ni) begin
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mmu_paddr <= '0;
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translation_valid <= '0;
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end else begin
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mmu_paddr <= mmu_vaddr_plen;
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translation_valid <= translation_req;
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end
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end
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end
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logic store_buffer_empty;
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// ------------------
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// Store Unit
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// ------------------
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store_unit #(
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.CVA6Cfg ( CVA6Cfg )
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) i_store_unit (
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.clk_i,
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.rst_ni,
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.flush_i,
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.stall_st_pending_i,
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.no_st_pending_o,
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.store_buffer_empty_o ( store_buffer_empty ),
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.valid_i ( st_valid_i ),
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.lsu_ctrl_i ( lsu_ctrl ),
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.pop_st_o ( pop_st ),
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.commit_i,
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.commit_ready_o,
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.amo_valid_commit_i,
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.valid_o ( st_valid ),
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.trans_id_o ( st_trans_id ),
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.result_o ( st_result ),
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.ex_o ( st_ex ),
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// MMU port
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.translation_req_o ( st_translation_req ),
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.vaddr_o ( st_vaddr ),
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.mem_paddr_o ( mem_paddr_o ),
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.paddr_i ( mmu_paddr ),
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.ex_i ( mmu_exception ),
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.dtlb_hit_i ( dtlb_hit ),
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// Load Unit
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.page_offset_i ( page_offset ),
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.page_offset_matches_o ( page_offset_matches ),
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// AMOs
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.amo_req_o,
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.amo_resp_i,
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// to memory arbiter
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.req_port_i ( dcache_req_ports_i [2] ),
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.req_port_o ( dcache_req_ports_o [2] )
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);
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// ------------------
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// Load Unit
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// ------------------
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load_unit #(
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.CVA6Cfg ( CVA6Cfg ),
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.ArianeCfg ( ArianeCfg )
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) i_load_unit (
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.valid_i ( ld_valid_i ),
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.lsu_ctrl_i ( lsu_ctrl ),
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.pop_ld_o ( pop_ld ),
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.valid_o ( ld_valid ),
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.trans_id_o ( ld_trans_id ),
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.result_o ( ld_result ),
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.ex_o ( ld_ex ),
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// MMU port
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.translation_req_o ( ld_translation_req ),
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.vaddr_o ( ld_vaddr ),
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.paddr_i ( mmu_paddr ),
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.ex_i ( mmu_exception ),
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.dtlb_hit_i ( dtlb_hit ),
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.dtlb_ppn_i ( dtlb_ppn ),
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// to store unit
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.page_offset_o ( page_offset ),
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.page_offset_matches_i ( page_offset_matches ),
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.store_buffer_empty_i ( store_buffer_empty ),
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// to memory arbiter
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.req_port_i ( dcache_req_ports_i [1] ),
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.req_port_o ( dcache_req_ports_o [1] ),
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.dcache_wbuffer_not_ni_i,
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.commit_tran_id_i,
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.*
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);
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// ----------------------------
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// Output Pipeline Register
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// ----------------------------
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// amount of pipeline registers inserted for load/store return path
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// can be tuned to trade-off IPC vs. cycle time
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shift_reg #(
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.dtype ( logic[$bits(ld_valid) + $bits(ld_trans_id) + $bits(ld_result) + $bits(ld_ex) - 1: 0]),
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.Depth ( cva6_config_pkg::CVA6ConfigNrLoadPipeRegs )
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) i_pipe_reg_load (
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.clk_i,
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.rst_ni,
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.d_i ( {ld_valid, ld_trans_id, ld_result, ld_ex} ),
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.d_o ( {load_valid_o, load_trans_id_o, load_result_o, load_exception_o} )
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);
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shift_reg #(
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.dtype ( logic[$bits(st_valid) + $bits(st_trans_id) + $bits(st_result) + $bits(st_ex) - 1: 0]),
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.Depth ( cva6_config_pkg::CVA6ConfigNrStorePipeRegs )
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) i_pipe_reg_store (
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.clk_i,
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.rst_ni,
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.d_i ( {st_valid, st_trans_id, st_result, st_ex} ),
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.d_o ( {store_valid_o, store_trans_id_o, store_result_o, store_exception_o} )
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);
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// determine whether this is a load or store
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always_comb begin : which_op
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ld_valid_i = 1'b0;
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st_valid_i = 1'b0;
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translation_req = 1'b0;
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mmu_vaddr = {riscv::VLEN{1'b0}};
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// check the operation to activate the right functional unit accordingly
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unique case (lsu_ctrl.fu)
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// all loads go here
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LOAD: begin
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ld_valid_i = lsu_ctrl.valid;
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translation_req = ld_translation_req;
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mmu_vaddr = ld_vaddr;
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end
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// all stores go here
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STORE: begin
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st_valid_i = lsu_ctrl.valid;
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translation_req = st_translation_req;
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mmu_vaddr = st_vaddr;
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end
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// not relevant for the LSU
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default: ;
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endcase
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end
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// ---------------
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// Byte Enable
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// ---------------
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// we can generate the byte enable from the virtual address since the last
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// 12 bit are the same anyway
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// and we can always generate the byte enable from the address at hand
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assign be_i = riscv::IS_XLEN64 ? be_gen(vaddr_i[2:0], extract_transfer_size(fu_data_i.operation)):
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be_gen_32(vaddr_i[1:0], extract_transfer_size(fu_data_i.operation));
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// ------------------------
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// Misaligned Exception
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// ------------------------
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// we can detect a misaligned exception immediately
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// the misaligned exception is passed to the functional unit via the MMU, which in case
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// can augment the exception if other memory related exceptions like a page fault or access errors
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always_comb begin : data_misaligned_detection
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misaligned_exception = {
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{riscv::XLEN{1'b0}},
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{riscv::XLEN{1'b0}},
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1'b0
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};
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data_misaligned = 1'b0;
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if (lsu_ctrl.valid) begin
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case (lsu_ctrl.operation)
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// double word
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LD, SD, FLD, FSD,
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AMO_LRD, AMO_SCD,
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AMO_SWAPD, AMO_ADDD, AMO_ANDD, AMO_ORD,
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AMO_XORD, AMO_MAXD, AMO_MAXDU, AMO_MIND,
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AMO_MINDU: begin
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if (lsu_ctrl.vaddr[2:0] != 3'b000) begin
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data_misaligned = 1'b1;
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end
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end
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// word
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LW, LWU, SW, FLW, FSW,
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AMO_LRW, AMO_SCW,
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AMO_SWAPW, AMO_ADDW, AMO_ANDW, AMO_ORW,
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AMO_XORW, AMO_MAXW, AMO_MAXWU, AMO_MINW,
|
|
AMO_MINWU: begin
|
|
if (lsu_ctrl.vaddr[1:0] != 2'b00) begin
|
|
data_misaligned = 1'b1;
|
|
end
|
|
end
|
|
// half word
|
|
LH, LHU, SH, FLH, FSH: begin
|
|
if (lsu_ctrl.vaddr[0] != 1'b0) begin
|
|
data_misaligned = 1'b1;
|
|
end
|
|
end
|
|
// byte -> is always aligned
|
|
default:;
|
|
endcase
|
|
end
|
|
|
|
if (data_misaligned) begin
|
|
|
|
if (lsu_ctrl.fu == LOAD) begin
|
|
misaligned_exception = {
|
|
riscv::LD_ADDR_MISALIGNED,
|
|
{{riscv::XLEN-riscv::VLEN{1'b0}},lsu_ctrl.vaddr},
|
|
1'b1
|
|
};
|
|
|
|
end else if (lsu_ctrl.fu == STORE) begin
|
|
misaligned_exception = {
|
|
riscv::ST_ADDR_MISALIGNED,
|
|
{{riscv::XLEN-riscv::VLEN{1'b0}},lsu_ctrl.vaddr},
|
|
1'b1
|
|
};
|
|
end
|
|
end
|
|
|
|
if (en_ld_st_translation_i && lsu_ctrl.overflow) begin
|
|
|
|
if (lsu_ctrl.fu == LOAD) begin
|
|
misaligned_exception = {
|
|
riscv::LD_ACCESS_FAULT,
|
|
{{riscv::XLEN-riscv::VLEN{1'b0}},lsu_ctrl.vaddr},
|
|
1'b1
|
|
};
|
|
|
|
end else if (lsu_ctrl.fu == STORE) begin
|
|
misaligned_exception = {
|
|
riscv::ST_ACCESS_FAULT,
|
|
{{riscv::XLEN-riscv::VLEN{1'b0}},lsu_ctrl.vaddr},
|
|
1'b1
|
|
};
|
|
end
|
|
end
|
|
end
|
|
|
|
// ------------------
|
|
// LSU Control
|
|
// ------------------
|
|
// new data arrives here
|
|
lsu_ctrl_t lsu_req_i;
|
|
|
|
assign lsu_req_i = {lsu_valid_i, vaddr_i, overflow, fu_data_i.operand_b, be_i, fu_data_i.fu, fu_data_i.operation, fu_data_i.trans_id};
|
|
|
|
lsu_bypass #(
|
|
.CVA6Cfg ( CVA6Cfg )
|
|
) lsu_bypass_i (
|
|
.lsu_req_i ( lsu_req_i ),
|
|
.lsu_req_valid_i ( lsu_valid_i ),
|
|
.pop_ld_i ( pop_ld ),
|
|
.pop_st_i ( pop_st ),
|
|
|
|
.lsu_ctrl_o ( lsu_ctrl ),
|
|
.ready_o ( lsu_ready_o ),
|
|
.*
|
|
);
|
|
|
|
assign lsu_addr_o = lsu_ctrl.vaddr;
|
|
assign lsu_rmask_o = lsu_ctrl.fu == LOAD ? lsu_ctrl.be : '0;
|
|
assign lsu_wmask_o = lsu_ctrl.fu == STORE ? lsu_ctrl.be : '0;
|
|
assign lsu_addr_trans_id_o = lsu_ctrl.trans_id;
|
|
|
|
endmodule
|
|
|