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* Clean-up README.md and top-level directory This removes the duplicate `scripts` and `util` directories. Furthermore the README is condensed by collapsing the citation and adding the CITATION file to the repository. Signed-off-by: Florian Zaruba <florian@openhwgroup.org> * Re-name icache req/rsp structs The structs used to communicate with the icache have contained the direction, which makes no sense for structs since they inherently don't have any direction. Signed-off-by: Florian Zaruba <florian@openhwgroup.org> --------- Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
465 lines
22 KiB
Systemverilog
465 lines
22 KiB
Systemverilog
// Copyright 2018 ETH Zurich and University of Bologna.
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// Copyright and related rights are licensed under the Solderpad Hardware
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// License, Version 0.51 (the "License"); you may not use this file except in
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// compliance with the License. You may obtain a copy of the License at
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// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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// or agreed to in writing, software, hardware and materials distributed under
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// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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// CONDITIONS OF ANY KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations under the License.
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//
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// Author: Florian Zaruba, ETH Zurich
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// Date: 19/04/2017
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// Description: Memory Management Unit for Ariane, contains TLB and
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// address translation unit. SV39 as defined in RISC-V
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// privilege specification 1.11-WIP
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module mmu import ariane_pkg::*; #(
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parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
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parameter int unsigned INSTR_TLB_ENTRIES = 4,
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parameter int unsigned DATA_TLB_ENTRIES = 4,
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parameter int unsigned ASID_WIDTH = 1,
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parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig
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) (
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input logic clk_i,
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input logic rst_ni,
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input logic flush_i,
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input logic enable_translation_i,
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input logic en_ld_st_translation_i, // enable virtual memory translation for load/stores
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// IF interface
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input icache_arsp_t icache_areq_i,
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output icache_areq_t icache_areq_o,
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// LSU interface
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// this is a more minimalistic interface because the actual addressing logic is handled
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// in the LSU as we distinguish load and stores, what we do here is simple address translation
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input exception_t misaligned_ex_i,
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input logic lsu_req_i, // request address translation
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input logic [riscv::VLEN-1:0] lsu_vaddr_i, // virtual address in
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input logic lsu_is_store_i, // the translation is requested by a store
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// if we need to walk the page table we can't grant in the same cycle
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// Cycle 0
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output logic lsu_dtlb_hit_o, // sent in the same cycle as the request if translation hits in the DTLB
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output logic [riscv::PPNW-1:0] lsu_dtlb_ppn_o, // ppn (send same cycle as hit)
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// Cycle 1
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output logic lsu_valid_o, // translation is valid
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output logic [riscv::PLEN-1:0] lsu_paddr_o, // translated address
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output exception_t lsu_exception_o, // address translation threw an exception
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// General control signals
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input riscv::priv_lvl_t priv_lvl_i,
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input riscv::priv_lvl_t ld_st_priv_lvl_i,
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input logic sum_i,
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input logic mxr_i,
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// input logic flag_mprv_i,
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input logic [riscv::PPNW-1:0] satp_ppn_i,
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input logic [ASID_WIDTH-1:0] asid_i,
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input logic [ASID_WIDTH-1:0] asid_to_be_flushed_i,
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input logic [riscv::VLEN-1:0] vaddr_to_be_flushed_i,
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input logic flush_tlb_i,
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// Performance counters
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output logic itlb_miss_o,
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output logic dtlb_miss_o,
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// PTW memory interface
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input dcache_req_o_t req_port_i,
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output dcache_req_i_t req_port_o,
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// PMP
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input riscv::pmpcfg_t [15:0] pmpcfg_i,
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input logic [15:0][riscv::PLEN-3:0] pmpaddr_i
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);
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logic iaccess_err; // insufficient privilege to access this instruction page
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logic daccess_err; // insufficient privilege to access this data page
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logic ptw_active; // PTW is currently walking a page table
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logic walking_instr; // PTW is walking because of an ITLB miss
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logic ptw_error; // PTW threw an exception
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logic ptw_access_exception; // PTW threw an access exception (PMPs)
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logic [riscv::PLEN-1:0] ptw_bad_paddr; // PTW PMP exception bad physical addr
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logic [riscv::VLEN-1:0] update_vaddr;
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tlb_update_t update_ptw_itlb, update_ptw_dtlb;
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logic itlb_lu_access;
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riscv::pte_t itlb_content;
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logic itlb_is_2M;
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logic itlb_is_1G;
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logic itlb_lu_hit;
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logic dtlb_lu_access;
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riscv::pte_t dtlb_content;
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logic dtlb_is_2M;
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logic dtlb_is_1G;
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logic dtlb_lu_hit;
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// Assignments
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assign itlb_lu_access = icache_areq_i.fetch_req;
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assign dtlb_lu_access = lsu_req_i;
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tlb #(
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.CVA6Cfg ( CVA6Cfg ),
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.TLB_ENTRIES ( INSTR_TLB_ENTRIES ),
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.ASID_WIDTH ( ASID_WIDTH )
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) i_itlb (
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.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
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.flush_i ( flush_tlb_i ),
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.update_i ( update_ptw_itlb ),
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.lu_access_i ( itlb_lu_access ),
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.lu_asid_i ( asid_i ),
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.asid_to_be_flushed_i ( asid_to_be_flushed_i ),
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.vaddr_to_be_flushed_i ( vaddr_to_be_flushed_i ),
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.lu_vaddr_i ( icache_areq_i.fetch_vaddr ),
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.lu_content_o ( itlb_content ),
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.lu_is_2M_o ( itlb_is_2M ),
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.lu_is_1G_o ( itlb_is_1G ),
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.lu_hit_o ( itlb_lu_hit )
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);
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tlb #(
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.CVA6Cfg ( CVA6Cfg ),
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.TLB_ENTRIES ( DATA_TLB_ENTRIES ),
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.ASID_WIDTH ( ASID_WIDTH )
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) i_dtlb (
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.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
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.flush_i ( flush_tlb_i ),
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.update_i ( update_ptw_dtlb ),
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.lu_access_i ( dtlb_lu_access ),
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.lu_asid_i ( asid_i ),
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.asid_to_be_flushed_i ( asid_to_be_flushed_i ),
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.vaddr_to_be_flushed_i ( vaddr_to_be_flushed_i ),
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.lu_vaddr_i ( lsu_vaddr_i ),
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.lu_content_o ( dtlb_content ),
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.lu_is_2M_o ( dtlb_is_2M ),
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.lu_is_1G_o ( dtlb_is_1G ),
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.lu_hit_o ( dtlb_lu_hit )
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);
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ptw #(
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.CVA6Cfg ( CVA6Cfg ),
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.ASID_WIDTH ( ASID_WIDTH ),
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.ArianeCfg ( ArianeCfg )
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) i_ptw (
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.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
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.ptw_active_o ( ptw_active ),
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.walking_instr_o ( walking_instr ),
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.ptw_error_o ( ptw_error ),
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.ptw_access_exception_o ( ptw_access_exception ),
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.enable_translation_i ( enable_translation_i ),
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.update_vaddr_o ( update_vaddr ),
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.itlb_update_o ( update_ptw_itlb ),
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.dtlb_update_o ( update_ptw_dtlb ),
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.itlb_access_i ( itlb_lu_access ),
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.itlb_hit_i ( itlb_lu_hit ),
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.itlb_vaddr_i ( icache_areq_i.fetch_vaddr ),
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.dtlb_access_i ( dtlb_lu_access ),
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.dtlb_hit_i ( dtlb_lu_hit ),
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.dtlb_vaddr_i ( lsu_vaddr_i ),
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.req_port_i ( req_port_i ),
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.req_port_o ( req_port_o ),
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.pmpcfg_i,
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.pmpaddr_i,
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.bad_paddr_o ( ptw_bad_paddr ),
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.*
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);
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// ila_1 i_ila_1 (
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// .clk(clk_i), // input wire clk
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// .probe0({req_port_o.address_tag, req_port_o.address_index}),
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// .probe1(req_port_o.data_req), // input wire [63:0] probe1
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// .probe2(req_port_i.data_gnt), // input wire [0:0] probe2
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// .probe3(req_port_i.data_rdata), // input wire [0:0] probe3
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// .probe4(req_port_i.data_rvalid), // input wire [0:0] probe4
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// .probe5(ptw_error), // input wire [1:0] probe5
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// .probe6(update_vaddr), // input wire [0:0] probe6
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// .probe7(update_ptw_itlb.valid), // input wire [0:0] probe7
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// .probe8(update_ptw_dtlb.valid), // input wire [0:0] probe8
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// .probe9(dtlb_lu_access), // input wire [0:0] probe9
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// .probe10(lsu_vaddr_i), // input wire [0:0] probe10
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// .probe11(dtlb_lu_hit), // input wire [0:0] probe11
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// .probe12(itlb_lu_access), // input wire [0:0] probe12
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// .probe13(icache_areq_i.fetch_vaddr), // input wire [0:0] probe13
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// .probe14(itlb_lu_hit) // input wire [0:0] probe13
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// );
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//-----------------------
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// Instruction Interface
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//-----------------------
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logic match_any_execute_region;
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logic pmp_instr_allow;
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// The instruction interface is a simple request response interface
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always_comb begin : instr_interface
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// MMU disabled: just pass through
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icache_areq_o.fetch_valid = icache_areq_i.fetch_req;
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icache_areq_o.fetch_paddr = icache_areq_i.fetch_vaddr[riscv::PLEN-1:0]; // play through in case we disabled address translation
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// two potential exception sources:
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// 1. HPTW threw an exception -> signal with a page fault exception
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// 2. We got an access error because of insufficient permissions -> throw an access exception
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icache_areq_o.fetch_exception = '0;
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// Check whether we are allowed to access this memory region from a fetch perspective
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iaccess_err = icache_areq_i.fetch_req && enable_translation_i
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&& (((priv_lvl_i == riscv::PRIV_LVL_U) && ~itlb_content.u)
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|| ((priv_lvl_i == riscv::PRIV_LVL_S) && itlb_content.u));
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// MMU enabled: address from TLB, request delayed until hit. Error when TLB
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// hit and no access right or TLB hit and translated address not valid (e.g.
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// AXI decode error), or when PTW performs walk due to ITLB miss and raises
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// an error.
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if (enable_translation_i) begin
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// we work with SV39 or SV32, so if VM is enabled, check that all bits [riscv::VLEN-1:riscv::SV-1] are equal
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if (icache_areq_i.fetch_req && !((&icache_areq_i.fetch_vaddr[riscv::VLEN-1:riscv::SV-1]) == 1'b1 || (|icache_areq_i.fetch_vaddr[riscv::VLEN-1:riscv::SV-1]) == 1'b0)) begin
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icache_areq_o.fetch_exception = {riscv::INSTR_ACCESS_FAULT, {{riscv::XLEN-riscv::VLEN{1'b0}}, icache_areq_i.fetch_vaddr}, 1'b1};
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end
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icache_areq_o.fetch_valid = 1'b0;
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// 4K page
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icache_areq_o.fetch_paddr = {itlb_content.ppn, icache_areq_i.fetch_vaddr[11:0]};
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// Mega page
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if (itlb_is_2M) begin
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icache_areq_o.fetch_paddr[20:12] = icache_areq_i.fetch_vaddr[20:12];
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end
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// Giga page
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if (itlb_is_1G) begin
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icache_areq_o.fetch_paddr[29:12] = icache_areq_i.fetch_vaddr[29:12];
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end
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// ---------
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// ITLB Hit
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// --------
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// if we hit the ITLB output the request signal immediately
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if (itlb_lu_hit) begin
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icache_areq_o.fetch_valid = icache_areq_i.fetch_req;
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// we got an access error
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if (iaccess_err) begin
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// throw a page fault
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icache_areq_o.fetch_exception = {riscv::INSTR_PAGE_FAULT, {{riscv::XLEN-riscv::VLEN{1'b0}}, icache_areq_i.fetch_vaddr}, 1'b1};
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end else if (!pmp_instr_allow) begin
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icache_areq_o.fetch_exception = {riscv::INSTR_ACCESS_FAULT, {{riscv::XLEN-riscv::PLEN{1'b0}}, icache_areq_i.fetch_vaddr}, 1'b1};
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end
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end else
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// ---------
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// ITLB Miss
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// ---------
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// watch out for exceptions happening during walking the page table
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if (ptw_active && walking_instr) begin
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icache_areq_o.fetch_valid = ptw_error | ptw_access_exception;
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if (ptw_error) icache_areq_o.fetch_exception = {riscv::INSTR_PAGE_FAULT, {{riscv::XLEN-riscv::VLEN{1'b0}}, update_vaddr}, 1'b1};
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// TODO(moschn,zarubaf): What should the value of tval be in this case?
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else icache_areq_o.fetch_exception = {riscv::INSTR_ACCESS_FAULT, {{riscv::XLEN-riscv::PLEN{1'b0}}, ptw_bad_paddr}, 1'b1};
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end
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end
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// if it didn't match any execute region throw an `Instruction Access Fault`
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// or: if we are not translating, check PMPs immediately on the paddr
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if ((!match_any_execute_region && !ptw_error) || (!enable_translation_i && !pmp_instr_allow)) begin
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icache_areq_o.fetch_exception = {riscv::INSTR_ACCESS_FAULT, {{riscv::XLEN-riscv::PLEN{1'b0}}, icache_areq_o.fetch_paddr}, 1'b1};
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end
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end
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// check for execute flag on memory
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assign match_any_execute_region = ariane_pkg::is_inside_execute_regions(ArianeCfg, {{64-riscv::PLEN{1'b0}}, icache_areq_o.fetch_paddr});
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// Instruction fetch
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pmp #(
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.CVA6Cfg ( CVA6Cfg ),
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.PLEN ( riscv::PLEN ),
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.PMP_LEN ( riscv::PLEN - 2 ),
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.NR_ENTRIES ( ArianeCfg.NrPMPEntries )
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) i_pmp_if (
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.addr_i ( icache_areq_o.fetch_paddr ),
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.priv_lvl_i,
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// we will always execute on the instruction fetch port
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.access_type_i ( riscv::ACCESS_EXEC ),
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// Configuration
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.conf_addr_i ( pmpaddr_i ),
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.conf_i ( pmpcfg_i ),
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.allow_o ( pmp_instr_allow )
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);
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//-----------------------
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// Data Interface
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//-----------------------
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logic [riscv::VLEN-1:0] lsu_vaddr_n, lsu_vaddr_q;
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riscv::pte_t dtlb_pte_n, dtlb_pte_q;
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exception_t misaligned_ex_n, misaligned_ex_q;
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logic lsu_req_n, lsu_req_q;
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logic lsu_is_store_n, lsu_is_store_q;
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logic dtlb_hit_n, dtlb_hit_q;
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logic dtlb_is_2M_n, dtlb_is_2M_q;
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logic dtlb_is_1G_n, dtlb_is_1G_q;
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// check if we need to do translation or if we are always ready (e.g.: we are not translating anything)
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assign lsu_dtlb_hit_o = (en_ld_st_translation_i) ? dtlb_lu_hit : 1'b1;
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// Wires to PMP checks
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riscv::pmp_access_t pmp_access_type;
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logic pmp_data_allow;
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localparam PPNWMin = (riscv::PPNW-1 > 29) ? 29 : riscv::PPNW-1;
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// The data interface is simpler and only consists of a request/response interface
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always_comb begin : data_interface
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// save request and DTLB response
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lsu_vaddr_n = lsu_vaddr_i;
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lsu_req_n = lsu_req_i;
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misaligned_ex_n = misaligned_ex_i;
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dtlb_pte_n = dtlb_content;
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dtlb_hit_n = dtlb_lu_hit;
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lsu_is_store_n = lsu_is_store_i;
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dtlb_is_2M_n = dtlb_is_2M;
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dtlb_is_1G_n = dtlb_is_1G;
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lsu_paddr_o = lsu_vaddr_q[riscv::PLEN-1:0];
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lsu_dtlb_ppn_o = lsu_vaddr_n[riscv::PLEN-1:12];
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lsu_valid_o = lsu_req_q;
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lsu_exception_o = misaligned_ex_q;
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pmp_access_type = lsu_is_store_q ? riscv::ACCESS_WRITE : riscv::ACCESS_READ;
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// mute misaligned exceptions if there is no request otherwise they will throw accidental exceptions
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misaligned_ex_n.valid = misaligned_ex_i.valid & lsu_req_i;
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// Check if the User flag is set, then we may only access it in supervisor mode
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// if SUM is enabled
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daccess_err = en_ld_st_translation_i && ((ld_st_priv_lvl_i == riscv::PRIV_LVL_S && !sum_i && dtlb_pte_q.u) || // SUM is not set and we are trying to access a user page in supervisor mode
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(ld_st_priv_lvl_i == riscv::PRIV_LVL_U && !dtlb_pte_q.u)); // this is not a user page but we are in user mode and trying to access it
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// translation is enabled and no misaligned exception occurred
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if (en_ld_st_translation_i && !misaligned_ex_q.valid) begin
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lsu_valid_o = 1'b0;
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// 4K page
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lsu_paddr_o = {dtlb_pte_q.ppn, lsu_vaddr_q[11:0]};
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lsu_dtlb_ppn_o = dtlb_content.ppn;
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// Mega page
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if (dtlb_is_2M_q) begin
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lsu_paddr_o[20:12] = lsu_vaddr_q[20:12];
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lsu_dtlb_ppn_o[20:12] = lsu_vaddr_n[20:12];
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end
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// Giga page
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if (dtlb_is_1G_q) begin
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lsu_paddr_o[PPNWMin:12] = lsu_vaddr_q[PPNWMin:12];
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lsu_dtlb_ppn_o[PPNWMin:12] = lsu_vaddr_n[PPNWMin:12];
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end
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// ---------
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// DTLB Hit
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// --------
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if (dtlb_hit_q && lsu_req_q) begin
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lsu_valid_o = 1'b1;
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// exception priority:
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// PAGE_FAULTS have higher priority than ACCESS_FAULTS
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// virtual memory based exceptions are PAGE_FAULTS
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// physical memory based exceptions are ACCESS_FAULTS (PMA/PMP)
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// this is a store
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if (lsu_is_store_q) begin
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// check if the page is write-able and we are not violating privileges
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// also check if the dirty flag is set
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if (!dtlb_pte_q.w || daccess_err || !dtlb_pte_q.d) begin
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lsu_exception_o = {riscv::STORE_PAGE_FAULT, {{riscv::XLEN-riscv::VLEN{lsu_vaddr_q[riscv::VLEN-1]}},lsu_vaddr_q}, 1'b1};
|
|
// Check if any PMPs are violated
|
|
end else if (!pmp_data_allow) begin
|
|
lsu_exception_o = {riscv::ST_ACCESS_FAULT, {{riscv::XLEN-riscv::PLEN{1'b0}}, lsu_paddr_o}, 1'b1};
|
|
end
|
|
|
|
// this is a load
|
|
end else begin
|
|
// check for sufficient access privileges - throw a page fault if necessary
|
|
if (daccess_err) begin
|
|
lsu_exception_o = {riscv::LOAD_PAGE_FAULT, {{riscv::XLEN-riscv::VLEN{lsu_vaddr_q[riscv::VLEN-1]}},lsu_vaddr_q}, 1'b1};
|
|
// Check if any PMPs are violated
|
|
end else if (!pmp_data_allow) begin
|
|
lsu_exception_o = {riscv::LD_ACCESS_FAULT, {{riscv::XLEN-riscv::PLEN{1'b0}}, lsu_paddr_o}, 1'b1};
|
|
end
|
|
end
|
|
end else
|
|
|
|
// ---------
|
|
// DTLB Miss
|
|
// ---------
|
|
// watch out for exceptions
|
|
if (ptw_active && !walking_instr) begin
|
|
// page table walker threw an exception
|
|
if (ptw_error) begin
|
|
// an error makes the translation valid
|
|
lsu_valid_o = 1'b1;
|
|
// the page table walker can only throw page faults
|
|
if (lsu_is_store_q) begin
|
|
lsu_exception_o = {riscv::STORE_PAGE_FAULT, {{riscv::XLEN-riscv::VLEN{lsu_vaddr_q[riscv::VLEN-1]}},update_vaddr}, 1'b1};
|
|
end else begin
|
|
lsu_exception_o = {riscv::LOAD_PAGE_FAULT, {{riscv::XLEN-riscv::VLEN{lsu_vaddr_q[riscv::VLEN-1]}},update_vaddr}, 1'b1};
|
|
end
|
|
end
|
|
|
|
if (ptw_access_exception) begin
|
|
// an error makes the translation valid
|
|
lsu_valid_o = 1'b1;
|
|
// Any fault of the page table walk should be based of the original access type
|
|
if (lsu_is_store_q) begin
|
|
lsu_exception_o = {riscv::ST_ACCESS_FAULT, {{riscv::XLEN-riscv::VLEN{1'b0}}, lsu_vaddr_n}, 1'b1};
|
|
end else begin
|
|
lsu_exception_o = {riscv::LD_ACCESS_FAULT, {{riscv::XLEN-riscv::VLEN{1'b0}}, lsu_vaddr_n}, 1'b1};
|
|
end
|
|
end
|
|
end
|
|
end
|
|
// If translation is not enabled, check the paddr immediately against PMPs
|
|
else if (lsu_req_q && !misaligned_ex_q.valid && !pmp_data_allow) begin
|
|
if (lsu_is_store_q) begin
|
|
lsu_exception_o = {riscv::ST_ACCESS_FAULT, {{riscv::XLEN-riscv::PLEN{1'b0}}, lsu_paddr_o}, 1'b1};
|
|
end else begin
|
|
lsu_exception_o = {riscv::LD_ACCESS_FAULT, {{riscv::XLEN-riscv::PLEN{1'b0}}, lsu_paddr_o}, 1'b1};
|
|
end
|
|
end
|
|
end
|
|
|
|
// Load/store PMP check
|
|
pmp #(
|
|
.CVA6Cfg ( CVA6Cfg ),
|
|
.PLEN ( riscv::PLEN ),
|
|
.PMP_LEN ( riscv::PLEN - 2 ),
|
|
.NR_ENTRIES ( ArianeCfg.NrPMPEntries )
|
|
) i_pmp_data (
|
|
.addr_i ( lsu_paddr_o ),
|
|
.priv_lvl_i ( ld_st_priv_lvl_i ),
|
|
.access_type_i ( pmp_access_type ),
|
|
// Configuration
|
|
.conf_addr_i ( pmpaddr_i ),
|
|
.conf_i ( pmpcfg_i ),
|
|
.allow_o ( pmp_data_allow )
|
|
);
|
|
|
|
// ----------
|
|
// Registers
|
|
// ----------
|
|
always_ff @(posedge clk_i or negedge rst_ni) begin
|
|
if (~rst_ni) begin
|
|
lsu_vaddr_q <= '0;
|
|
lsu_req_q <= '0;
|
|
misaligned_ex_q <= '0;
|
|
dtlb_pte_q <= '0;
|
|
dtlb_hit_q <= '0;
|
|
lsu_is_store_q <= '0;
|
|
dtlb_is_2M_q <= '0;
|
|
dtlb_is_1G_q <= '0;
|
|
end else begin
|
|
lsu_vaddr_q <= lsu_vaddr_n;
|
|
lsu_req_q <= lsu_req_n;
|
|
misaligned_ex_q <= misaligned_ex_n;
|
|
dtlb_pte_q <= dtlb_pte_n;
|
|
dtlb_hit_q <= dtlb_hit_n;
|
|
lsu_is_store_q <= lsu_is_store_n;
|
|
dtlb_is_2M_q <= dtlb_is_2M_n;
|
|
dtlb_is_1G_q <= dtlb_is_1G_n;
|
|
end
|
|
end
|
|
endmodule
|