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dc103cd49f
* Clean-up README.md and top-level directory This removes the duplicate `scripts` and `util` directories. Furthermore the README is condensed by collapsing the citation and adding the CITATION file to the repository. Signed-off-by: Florian Zaruba <florian@openhwgroup.org> * Re-name icache req/rsp structs The structs used to communicate with the icache have contained the direction, which makes no sense for structs since they inherently don't have any direction. Signed-off-by: Florian Zaruba <florian@openhwgroup.org> --------- Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
179 lines
9.5 KiB
Systemverilog
179 lines
9.5 KiB
Systemverilog
// Copyright 2018 ETH Zurich and University of Bologna.
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// Copyright and related rights are licensed under the Solderpad Hardware
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// License, Version 0.51 (the "License"); you may not use this file except in
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// compliance with the License. You may obtain a copy of the License at
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// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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// or agreed to in writing, software, hardware and materials distributed under
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// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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// CONDITIONS OF ANY KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations under the License.
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//
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// Author: Florian Zaruba, ETH Zurich
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// Date: 06.10.2017
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// Description: Performance counters
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module perf_counters import ariane_pkg::*; #(
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parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
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parameter int unsigned NumPorts = 3 // number of miss ports
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) (
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input logic clk_i,
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input logic rst_ni,
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input logic debug_mode_i, // debug mode
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// SRAM like interface
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input logic [11:0] addr_i, // read/write address (up to 6 counters possible)
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input logic we_i, // write enable
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input riscv::xlen_t data_i, // data to write
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output riscv::xlen_t data_o, // data to read
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// from commit stage
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input scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i, // the instruction we want to commit
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input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i, // acknowledge that we are indeed committing
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// from L1 caches
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input logic l1_icache_miss_i,
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input logic l1_dcache_miss_i,
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// from MMU
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input logic itlb_miss_i,
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input logic dtlb_miss_i,
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// from issue stage
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input logic sb_full_i,
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// from frontend
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input logic if_empty_i,
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// from PC Gen
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input exception_t ex_i,
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input logic eret_i,
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input bp_resolve_t resolved_branch_i,
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// for newly added events
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input exception_t branch_exceptions_i, //Branch exceptions->execute unit-> branch_exception_o
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input icache_dreq_t l1_icache_access_i,
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input dcache_req_i_t[2:0] l1_dcache_access_i,
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input logic [NumPorts-1:0][DCACHE_SET_ASSOC-1:0]miss_vld_bits_i, //For Cache eviction (3ports-LOAD,STORE,PTW)
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input logic i_tlb_flush_i,
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input logic stall_issue_i, //stall-read operands
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input logic[31:0] mcountinhibit_i
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);
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logic [63:0] generic_counter_d[6:1];
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logic [63:0] generic_counter_q[6:1];
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//internal signal to keep track of exception
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logic read_access_exception,update_access_exception;
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logic events[6:1];
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//internal signal for MUX select line input
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logic [4:0] mhpmevent_d[6:1];
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logic [4:0] mhpmevent_q[6:1];
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//Multiplexer
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always_comb begin : Mux
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events[6:1]='{default:0};
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for(int unsigned i = 1; i <= 6; i++) begin
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case(mhpmevent_q[i])
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5'b00000 : events[i] = 0;
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5'b00001 : events[i] = l1_icache_miss_i;//L1 I-Cache misses
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5'b00010 : events[i] = l1_dcache_miss_i;//L1 D-Cache misses
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5'b00011 : events[i] = itlb_miss_i;//ITLB misses
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5'b00100 : events[i] = dtlb_miss_i;//DTLB misses
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5'b00101 : for (int unsigned j = 0; j < CVA6Cfg.NrCommitPorts; j++) if (commit_ack_i[j]) events[i] = commit_instr_i[j].fu == LOAD;//Load accesses
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5'b00110 : for (int unsigned j = 0; j < CVA6Cfg.NrCommitPorts; j++) if (commit_ack_i[j]) events[i] = commit_instr_i[j].fu == STORE;//Store accesses
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5'b00111 : events[i] = ex_i.valid;//Exceptions
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5'b01000 : events[i] = eret_i;//Exception handler returns
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5'b01001 : for (int unsigned j = 0; j < CVA6Cfg.NrCommitPorts; j++) if (commit_ack_i[j]) events[i] = commit_instr_i[j].fu == CTRL_FLOW;//Branch instructions
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5'b01010 : events[i] = resolved_branch_i.valid && resolved_branch_i.is_mispredict;//Branch mispredicts
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5'b01011 : events[i] = branch_exceptions_i.valid;//Branch exceptions
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// The standard software calling convention uses register x1 to hold the return address on a call
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// the unconditional jump is decoded as ADD op
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5'b01100 : for (int unsigned j = 0; j < CVA6Cfg.NrCommitPorts; j++) if (commit_ack_i[j]) events[i] = commit_instr_i[j].fu == CTRL_FLOW && (commit_instr_i[j].op == ADD || commit_instr_i[j].op == JALR) && (commit_instr_i[j].rd == 'd1 || commit_instr_i[j].rd == 'd5);//Call
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5'b01101 : for (int unsigned j = 0; j < CVA6Cfg.NrCommitPorts; j++) if (commit_ack_i[j]) events[i] = commit_instr_i[j].op == JALR && commit_instr_i[j].rd == 'd0;//Return
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5'b01110 : events[i] = sb_full_i;//MSB Full
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5'b01111 : events[i] = if_empty_i;//Instruction fetch Empty
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5'b10000 : events[i] = l1_icache_access_i.req;//L1 I-Cache accesses
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5'b10001 : events[i] = l1_dcache_access_i[0].data_req || l1_dcache_access_i[1].data_req || l1_dcache_access_i[2].data_req;//L1 D-Cache accesses
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5'b10010 : events[i] = (l1_dcache_miss_i && miss_vld_bits_i[0] == 8'hFF) || (l1_dcache_miss_i && miss_vld_bits_i[1] == 8'hFF) || (l1_dcache_miss_i && miss_vld_bits_i[2] == 8'hFF);//eviction
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5'b10011 : events[i] = i_tlb_flush_i;//I-TLB flush
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5'b10100 : for (int unsigned j = 0; j < CVA6Cfg.NrCommitPorts; j++) if (commit_ack_i[j]) events[i] = commit_instr_i[j].fu == ALU || commit_instr_i[j].fu == MULT;//Integer instructions
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5'b10101 : for (int unsigned j = 0; j < CVA6Cfg.NrCommitPorts; j++) if (commit_ack_i[j]) events[i] = commit_instr_i[j].fu == FPU || commit_instr_i[j].fu == FPU_VEC;//Floating Point Instructions
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5'b10110 : events[i] = stall_issue_i;//Pipeline bubbles
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default: events[i] = 0;
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endcase
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end
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end
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always_comb begin : generic_counter
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generic_counter_d = generic_counter_q;
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data_o = 'b0;
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mhpmevent_d = mhpmevent_q;
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read_access_exception = 1'b0;
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update_access_exception = 1'b0;
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for(int unsigned i = 1; i <= 6; i++) begin
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if ((!debug_mode_i) && (!we_i)) begin
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if ((events[i]) == 1 && (!mcountinhibit_i[i+2]))begin
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generic_counter_d[i] = generic_counter_q[i] + 1'b1;end
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else begin
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generic_counter_d[i] = 'b0;end
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end
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end
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//Read
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unique case (addr_i)
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riscv::CSR_MHPM_COUNTER_3,
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riscv::CSR_MHPM_COUNTER_4,
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riscv::CSR_MHPM_COUNTER_5,
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riscv::CSR_MHPM_COUNTER_6,
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riscv::CSR_MHPM_COUNTER_7,
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riscv::CSR_MHPM_COUNTER_8 :begin if (riscv::XLEN == 32) data_o = generic_counter_q[addr_i-riscv::CSR_MHPM_COUNTER_3 + 1][31:0]; else data_o = generic_counter_q[addr_i-riscv::CSR_MHPM_COUNTER_3 + 1];end
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riscv::CSR_MHPM_COUNTER_3H,
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riscv::CSR_MHPM_COUNTER_4H,
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riscv::CSR_MHPM_COUNTER_5H,
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riscv::CSR_MHPM_COUNTER_6H,
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riscv::CSR_MHPM_COUNTER_7H,
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riscv::CSR_MHPM_COUNTER_8H :begin if (riscv::XLEN == 32) data_o = generic_counter_q[addr_i-riscv::CSR_MHPM_COUNTER_3H + 1][63:32]; else read_access_exception = 1'b1;end
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riscv::CSR_MHPM_EVENT_3,
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riscv::CSR_MHPM_EVENT_4,
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riscv::CSR_MHPM_EVENT_5,
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riscv::CSR_MHPM_EVENT_6,
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riscv::CSR_MHPM_EVENT_7,
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riscv::CSR_MHPM_EVENT_8 : data_o = mhpmevent_q[addr_i-riscv::CSR_MHPM_EVENT_3 + 1] ;
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default: data_o = 'b0;
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endcase
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//Write
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if(we_i) begin
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unique case(addr_i)
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riscv::CSR_MHPM_COUNTER_3,
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riscv::CSR_MHPM_COUNTER_4,
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riscv::CSR_MHPM_COUNTER_5,
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riscv::CSR_MHPM_COUNTER_6,
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riscv::CSR_MHPM_COUNTER_7,
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riscv::CSR_MHPM_COUNTER_8 :begin if (riscv::XLEN == 32) generic_counter_d[addr_i-riscv::CSR_MHPM_COUNTER_3 + 1][31:0] = data_i; else generic_counter_d[addr_i-riscv::CSR_MHPM_COUNTER_3 + 1] = data_i; end
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riscv::CSR_MHPM_COUNTER_3H,
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riscv::CSR_MHPM_COUNTER_4H,
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riscv::CSR_MHPM_COUNTER_5H,
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riscv::CSR_MHPM_COUNTER_6H,
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riscv::CSR_MHPM_COUNTER_7H,
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riscv::CSR_MHPM_COUNTER_8H :begin if (riscv::XLEN == 32) generic_counter_d[addr_i-riscv::CSR_MHPM_COUNTER_3H + 1][63:32] = data_i; else update_access_exception = 1'b1;end
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riscv::CSR_MHPM_EVENT_3,
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riscv::CSR_MHPM_EVENT_4,
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riscv::CSR_MHPM_EVENT_5,
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riscv::CSR_MHPM_EVENT_6,
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riscv::CSR_MHPM_EVENT_7,
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riscv::CSR_MHPM_EVENT_8 : mhpmevent_d[addr_i-riscv::CSR_MHPM_EVENT_3 + 1] = data_i;
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default: update_access_exception = 1'b1;
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endcase
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end
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end
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//Registers
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (!rst_ni) begin
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generic_counter_q <= '{default:0};
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mhpmevent_q <= '{default:0};
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end else begin
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generic_counter_q <= generic_counter_d;
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mhpmevent_q <= mhpmevent_d;
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end
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end
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endmodule
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