mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-06-27 17:00:57 -04:00
513bb91f82
Support Ara via a custom, parametrised accelerator interface.
cv64a6_imafdcv_sv39_config_pkg.sv enables V extension
Pre-processor constant ARIANE_ACCELERATOR_PORT enables the interface between CVA6 and Ara.
FPU is bumped to a SIMD-compatible version
Backwards compatibility should be preserved. Once this is merged, we will change the reference of Ara upstream CVA6.
-----
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
Co-authored-by: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
Co-authored-by: Matteo Perotti <mperotti@iis.ee.ethz.ch>
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
84 lines
1.7 KiB
YAML
84 lines
1.7 KiB
YAML
ariane:
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incdirs: [
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include,
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]
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files: [
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include/riscv_pkg.sv,
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src/debug/dm_pkg.sv,
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include/ariane_pkg.sv,
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include/std_cache_pkg.sv,
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src/util/instruction_tracer_if.sv,
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src/util/instruction_tracer_pkg.sv,
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src/alu.sv,
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src/ariane.sv,
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src/branch_unit.sv,
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src/cache_ctrl.sv,
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src/commit_stage.sv,
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src/compressed_decoder.sv,
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src/controller.sv,
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src/csr_buffer.sv,
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src/csr_regfile.sv,
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src/decoder.sv,
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src/ex_stage.sv,
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src/frontend/btb.sv,
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src/frontend/bht.sv,
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src/frontend/ras.sv,
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src/frontend/instr_scan.sv,
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src/frontend/frontend.sv,
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src/icache.sv,
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src/id_stage.sv,
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src/instr_realigner.sv,
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src/issue_read_operands.sv,
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src/issue_stage.sv,
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src/lfsr.sv,
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src/load_unit.sv,
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src/load_store_unit.sv,
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src/miss_handler.sv,
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src/mmu_sv39/mmu.sv,
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src/mmu_sv32/cva6_mmu_sv32.sv,
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src/mult.sv,
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src/nbdcache.sv,
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src/vdregs.sv,
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src/std_cache_subsystem.sv,
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src/sram_wrapper.sv,
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src/pcgen_stage.sv,
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src/perf_counters.sv,
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src/mmu_sv39/ptw.sv,
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src/mmu_sv32/cva6_ptw_sv32.sv,
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src/re_name.sv,
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src/scoreboard.sv,
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src/store_buffer.sv,
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src/store_unit.sv,
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src/mmu_sv39/tlb.sv,
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src/mmu_sv32/cva6_tlb_sv32.sv,
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src/acc_dispatcher.sv,
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src/debug/dm_csrs.sv,
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src/debug/dm_mem.sv,
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src/debug/dm_top.sv,
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src/debug/dmi_cdc.sv,
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src/debug/dmi_jtag.sv,
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src/debug/dmi_jtag_tap.sv,
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fpga/apb_timer/apb_timer.sv,
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fpga/apb_timer/timer.sv,
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]
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riscv_regfile_rtl:
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targets: [
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rtl,
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]
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incdirs: [
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include,
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]
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files: [
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src/ariane_regfile.sv,
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]
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riscv_regfile_fpga:
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targets: [
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xilinx,
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]
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incdirs: [
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include,
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]
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files: [
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src/ariane_regfile_ff.sv,
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]
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