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Adds support for Trace Interface or Trace Ingress Port (TIP) on CVA6 TIP is Interface between a RISC-V hart and the trace encoder It generates information about the instruction retired. The implementation is compliant with the Efficient Trace for RISC-V standard Version 2.0.2(https://github.com/riscv-non-isa/riscv-trace-spec/releases/download/v2.0.2/riscv-trace-spec-asciidoc.pdf), specifically: Chapter 4.1: Instruction Trace Interface Requirements Chapter 4.2: Instruction Trace Interface The current implementation supports the following TIP signals: iretire, itype, cause, tval, priv, iaddr, and time. For Instruction Type (itype) encoding, it supports the following: Exception, Interrupt, Exception or interrupt return, Nontaken branch, Taken branch, Uninferable jump. What I have been able to test so far: Simulation: Executed C binaries and observed the waveform of TIP. --------- Co-authored-by: root <darshak.sheladiya@sysgo.com> Co-authored-by: CHAUVON Guillaume <guillaume.chauvon@thalesgroup.com> Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
16 lines
391 B
C
16 lines
391 B
C
// Copyright (c) 2025 Thales DIS design services SAS
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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// Author: Maxime Colson - Thales
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// Date: 20/03/2025
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// Contributors:
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// Darshak Sheladiya, SYSGO GmbH
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// Umberto Laghi, UNIBO
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//This test will be improved by taking into account other scenarios
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void branch_test();
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int main(int argc, char* arg[]) {
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branch_test();
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return 0;
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}
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