mirror of
https://github.com/openhwgroup/cva6.git
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07df142624
* : Fix PITON_ARIANE define issues * Fix write-back / cache read collision issue in serpent dcache. * Add separate bootrom / device tree for openpiton (hardcoded for 1x1 tile config at the moment). * Bootrom generation update (better compatibility with older python versions), new bootrom for OpenPiton+Ariane. * Fix assertion in icache. * Correct JTAG timing constraints. * Fix parameter type in fpga toplevel (fix #168). * Remove conflicting bootrom from fpga file list. * This flushs the branch predictors when entering exception handlers in order to avoid speculative fetches from virtual addresses (to be improved with PMAs). * Fix byte offset of IPIs in CLINT * Disable DCache flushes on fence for write-through cache (not needed in that case) * Fix blocking assignments in ff process. * Fix register access issue in debug mode, only affects A0 (fix #179). * Fix multiple driver issue in PLIC * Do not assume replicated data in serpent dcache when reading from an NC region. * Another byte offset fix in IPIs (CLINT) * Add AXI64 compliance switch to dcache_mem * Fix genesys 2 constraints * Map serpent atomic requests onto AXI atomic/exclusive transactions. * Cleanup of AXI memory plumbing, add separate AXI adapter module. * Remove unneeded interface signals, increase wbuffer #pending tx * Fix verilator compilation issues in AXI adapter. * Delete unnecessary constraint * Delete duplicate module instance * Update gitlab CI script * Small fixes to make riscv atomics work with serpent_axi_adapter. * Update travis and gitlab-ci scripts * Register b responses for better timing. * Remove fpu div submodule, update Makefile paths and src lists * Constant bits in haltsum reduction must be 1 (AND reduction). * Switch to DTM from riscv-dbg submodule * Further cleanup fixes in AXI/serpent atomics * Bump riscv-dbg version
45 lines
1.6 KiB
Text
45 lines
1.6 KiB
Text
[submodule "src/axi_mem_if"]
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path = src/axi_mem_if
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url = https://github.com/pulp-platform/axi_mem_if.git
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[submodule "src/axi_node"]
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path = src/axi_node
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url = https://github.com/pulp-platform/axi_node.git
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[submodule "src/fpga-support"]
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path = src/fpga-support
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url = https://github.com/pulp-platform/fpga-support.git
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[submodule "src/common_cells"]
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path = src/common_cells
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url = https://github.com/pulp-platform/common_cells.git
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[submodule "src/axi"]
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path = src/axi
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url = https://github.com/pulp-platform/axi.git
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[submodule "src/register_interface"]
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path = src/register_interface
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url = https://github.com/pulp-platform/register_interface.git
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[submodule "fpga/src/apb_uart"]
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path = fpga/src/apb_uart
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url = https://github.com/pulp-platform/apb_uart.git
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[submodule "fpga/src/apb_node"]
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path = fpga/src/apb_node
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url = https://github.com/pulp-platform/apb_node.git
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[submodule "fpga/src/axi2apb"]
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path = fpga/src/axi2apb
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url = https://github.com/pulp-platform/axi2apb.git
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[submodule "fpga/src/axi_slice"]
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path = fpga/src/axi_slice
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url = https://github.com/pulp-platform/axi_slice.git
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[submodule "src/tech_cells_generic"]
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path = src/tech_cells_generic
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url = https://github.com/pulp-platform/tech_cells_generic.git
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[submodule "src/fpu"]
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path = src/fpu
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url = https://github.com/pulp-platform/fpnew.git
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[submodule "fpga/src/ariane-ethernet"]
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path = fpga/src/ariane-ethernet
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url = https://github.com/lowRISC/ariane-ethernet.git
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[submodule "src/axi_riscv_atomics"]
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path = src/axi_riscv_atomics
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url = https://github.com/pulp-platform/axi_riscv_atomics.git
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[submodule "src/riscv-dbg"]
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path = src/riscv-dbg
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url = https://github.com/pulp-platform/riscv-dbg.git
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