mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-21 12:47:11 -04:00
07df142624
* : Fix PITON_ARIANE define issues * Fix write-back / cache read collision issue in serpent dcache. * Add separate bootrom / device tree for openpiton (hardcoded for 1x1 tile config at the moment). * Bootrom generation update (better compatibility with older python versions), new bootrom for OpenPiton+Ariane. * Fix assertion in icache. * Correct JTAG timing constraints. * Fix parameter type in fpga toplevel (fix #168). * Remove conflicting bootrom from fpga file list. * This flushs the branch predictors when entering exception handlers in order to avoid speculative fetches from virtual addresses (to be improved with PMAs). * Fix byte offset of IPIs in CLINT * Disable DCache flushes on fence for write-through cache (not needed in that case) * Fix blocking assignments in ff process. * Fix register access issue in debug mode, only affects A0 (fix #179). * Fix multiple driver issue in PLIC * Do not assume replicated data in serpent dcache when reading from an NC region. * Another byte offset fix in IPIs (CLINT) * Add AXI64 compliance switch to dcache_mem * Fix genesys 2 constraints * Map serpent atomic requests onto AXI atomic/exclusive transactions. * Cleanup of AXI memory plumbing, add separate AXI adapter module. * Remove unneeded interface signals, increase wbuffer #pending tx * Fix verilator compilation issues in AXI adapter. * Delete unnecessary constraint * Delete duplicate module instance * Update gitlab CI script * Small fixes to make riscv atomics work with serpent_axi_adapter. * Update travis and gitlab-ci scripts * Register b responses for better timing. * Remove fpu div submodule, update Makefile paths and src lists * Constant bits in haltsum reduction must be 1 (AND reduction). * Switch to DTM from riscv-dbg submodule * Further cleanup fixes in AXI/serpent atomics * Bump riscv-dbg version
107 lines
3.7 KiB
YAML
107 lines
3.7 KiB
YAML
package:
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name: ariane
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authors: [ "Florian Zaruba <zarubaf@iis.ee.ethz.ch>" ]
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dependencies:
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axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.4.5 }
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axi_mem_if: { git: "https://github.com/pulp-platform/axi_mem_if.git", version: 0.2.0 }
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axi_node: { git: "https://github.com/pulp-platform/axi_node.git", version: 1.1.1 }
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tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.1.1 }
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common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.8.0 }
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fpga-support: { git: "https://github.com/pulp-platform/fpga-support.git", version: 0.3.2 }
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sources:
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- src/fpu/src/fpu_div_sqrt_mvp/hdl/fpu_ff.sv
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- src/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
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- src/fpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv
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- src/fpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv
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- src/fpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv
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- src/fpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv
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- src/fpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv
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- src/fpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv
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- src/fpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv
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- src/fpu/src/pkg/fpnew_pkg.vhd
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- src/fpu/src/pkg/fpnew_fmts_pkg.vhd
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- src/fpu/src/pkg/fpnew_comps_pkg.vhd
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- src/fpu/src/pkg/fpnew_pkg_constants.vhd
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- src/fpu/src/utils/fp_pipe.vhd
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- src/fpu/src/utils/fp_rounding.vhd
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- src/fpu/src/utils/fp_arbiter.vhd
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- src/fpu/src/ops/fma_core.vhd
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- src/fpu/src/ops/fp_fma.vhd
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- src/fpu/src/ops/fp_divsqrt_multi.vhd
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- src/fpu/src/ops/fp_noncomp.vhd
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- src/fpu/src/ops/fp_f2fcasts_fmt.vhd
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- src/fpu/src/ops/fp_f2icasts_fmt.vhd
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- src/fpu/src/ops/fp_i2fcasts_fmt.vhd
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- src/fpu/src/subunits/addmul_fmt_slice.vhd
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- src/fpu/src/subunits/addmul_block.vhd
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- src/fpu/src/subunits/divsqrt_multifmt_slice.vhd
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- src/fpu/src/subunits/divsqrt_block.vhd
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- src/fpu/src/subunits/noncomp_fmt_slice.vhd
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- src/fpu/src/subunits/noncomp_block.vhd
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- src/fpu/src/subunits/conv_fmt_slice.vhd
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- src/fpu/src/subunits/conv_ifmt_slice.vhd
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- src/fpu/src/subunits/conv_block.vhd
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- src/fpu/src/fpnew.vhd
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- src/fpu/src/fpnew_top.vhd
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- include/riscv_pkg.sv
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- src/debug/dm_pkg.sv
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- include/ariane_pkg.sv
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- include/std_cache_pkg.sv
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- target: not(synthesis)
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files:
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- src/util/instruction_tracer_pkg.sv
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- src/util/instruction_tracer_if.sv
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- src/alu.sv
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- src/fpu_wrap.sv
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- src/ariane.sv
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- src/branch_unit.sv
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- src/compressed_decoder.sv
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- src/controller.sv
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- src/csr_buffer.sv
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- src/csr_regfile.sv
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- src/decoder.sv
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- src/ex_stage.sv
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- src/frontend/btb.sv
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- src/frontend/bht.sv
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- src/frontend/ras.sv
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- src/frontend/instr_scan.sv
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- src/frontend/frontend.sv
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- src/id_stage.sv
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- src/instr_realigner.sv
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- src/issue_read_operands.sv
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- src/issue_stage.sv
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- src/load_unit.sv
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- src/load_store_unit.sv
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- src/mmu.sv
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- src/mult.sv
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- src/serdiv.sv
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- src/perf_counters.sv
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- src/ptw.sv
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- src/ariane_regfile_ff.sv
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# - src/ariane_regfile.sv
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- src/re_name.sv
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- src/scoreboard.sv
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- src/store_buffer.sv
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- src/amo_buffer.sv
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- src/store_unit.sv
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- src/tlb.sv
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- src/commit_stage.sv
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- src/axi_adapter.sv
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- src/cache_subsystem/cache_ctrl.sv
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- src/cache_subsystem/amo_alu.sv
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- src/cache_subsystem/miss_handler.sv
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- src/cache_subsystem/std_cache_subsystem.sv
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- src/cache_subsystem/std_icache.sv
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- src/cache_subsystem/std_nbdcache.sv
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- src/debug/debug_rom/debug_rom.sv
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- src/debug/dm_csrs.sv
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- src/clint/clint.sv
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- src/clint/axi_lite_interface.sv
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- src/debug/dm_mem.sv
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- src/debug/dm_top.sv
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- src/debug/dmi_cdc.sv
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- src/debug/dmi_jtag.sv
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- src/debug/dm_sba.sv
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- src/debug/dmi_jtag_tap.sv
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