mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-23 13:47:13 -04:00
a5f3184a65
* Add spike isa sim * Fix AMO problem in verilator * 🎨 Tidy up FPU wrapper * Bump axi_exclusive submodule * Refactor serpent AXI adapter, bump dbg and atomics submodules, add separate bootrom for linux on OpenPiton (#190) * Refactor serpent AXI adapter * Disable FPU in OpenPiton by default * Bump dbg and atomics submodules * Fix cache testbenches (interface change) * FPGA bootrom changes for OpenPiton SDHC * Introduce two bootroms, one for baremetal apps (pitonstream), and one for linux boot from SD * Testing barrier-based synchronisation instead of CLINT-based * This bootrom works for 2 core on g2 and if you change MAX_HARTS to 4, then 4 cores on vc707 * Add MAX_HARTS switch to makefile * Fix gitlab CI * Revert standard FPGA bootrom * Update Flist * Make UART_FREQ a parameter * Fix typo in tb.list and an error in define switch in ariane_pkg * Copy over SD-driver in bootloader from @leon575777642 * Fix compilation issues of bootrom * Change signal name in serpent periph portlist * Correct generate statement in serpent dcache memory * Add Piton SD Controller, FPGA fixes * Fix race condition in dcache misshandler * Add tandem spike to Make flow * Remove OpenPiton SD Card controller again
72 lines
2 KiB
Text
72 lines
2 KiB
Text
/dts-v1/;
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "eth,ariane-bare-dev";
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model = "eth,ariane-bare";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <32768>; // 32.768 kHz
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CPU0: cpu@0 {
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clock-frequency = <50000000>; // 50 MHz
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device_type = "cpu";
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reg = <0>;
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status = "okay";
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compatible = "eth, ariane", "riscv";
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riscv,isa = "rv64imafdc";
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mmu-type = "riscv,sv39";
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tlb-split;
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// HLIC - hart local interrupt controller
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CPU0_intc: interrupt-controller {
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0x0 0x10000000>;
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "eth,ariane-bare-soc", "simple-bus";
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ranges;
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clint@2000000 {
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compatible = "riscv,clint0";
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interrupts-extended = <&CPU0_intc 3 &CPU0_intc 7>;
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reg = <0x0 0x2000000 0x0 0xc0000>;
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reg-names = "control";
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};
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// PLIC needs to be disabeld for tandem verification
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// PLIC0: interrupt-controller@c000000 {
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// #address-cells = <0>;
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// #interrupt-cells = <1>;
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// compatible = "sifive,plic-1.0.0", "riscv,plic0";
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// interrupt-controller;
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// interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
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// reg = <0x0 0xc000000 0x0 0x4000000>;
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// riscv,max-priority = <7>;
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// riscv,ndev = <2>;
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// };
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debug-controller@0 {
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compatible = "riscv,debug-013";
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interrupts-extended = <&CPU0_intc 65535>;
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reg = <0x0 0x0 0x0 0x1000>;
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reg-names = "control";
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};
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uart@10000000 {
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compatible = "ns16750";
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reg = <0x0 0x10000000 0x0 0x1000>;
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clock-frequency = <50000000>;
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current-speed = <115200>;
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// interrupt-parent = <&PLIC0>;
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interrupts = <1>;
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reg-shift = <2>; // regs are spaced on 32 bit boundary
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reg-io-width = <4>; // only 32-bit access are supported
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};
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};
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};
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