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519 lines
28 KiB
Makefile
519 lines
28 KiB
Makefile
# Author: Florian Zaruba, ETH Zurich
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# Date: 03/19/2017
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# Description: Makefile for linting and testing Ariane.
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# questa library
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library ?= work
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# verilator lib
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ver-library ?= work-ver
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# library for DPI
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dpi-library ?= work-dpi
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# Top level module to compile
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top_level ?= ariane_tb
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# Maximum amount of cycles for a successful simulation run
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max_cycles ?= 10000000
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# Test case to run
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test_case ?= core_test
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# QuestaSim Version
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questa_version ?= ${QUESTASIM_VERSION}
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# verilator version
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verilator ?= verilator
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# traget option
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target-options ?=
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# additional definess
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defines ?= WT_DCACHE
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# test name for torture runs (binary name)
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test-location ?= output/test
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# set to either nothing or -log
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torture-logs :=
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# custom elf bin to run with sim or sim-verilator
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elf-bin ?= tmp/riscv-tests/build/benchmarks/dhrystone.riscv
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# root path
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mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST)))
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root-dir := $(dir $(mkfile_path))
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support_verilator_4 := $(shell (verilator --version | grep '4\.') &> /dev/null; echo $$?)
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ifeq ($(support_verilator_4), 0)
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verilator_threads := 2
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endif
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ifndef RISCV
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$(error RISCV not set - please point your RISCV variable to your RISCV installation)
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endif
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# spike tandem verification
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ifdef spike-tandem
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compile_flag += -define SPIKE_TANDEM
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ifndef preload
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$(error Tandem verification requires preloading)
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endif
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endif
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# Sources
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# Package files -> compile first
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ariane_pkg := include/riscv_pkg.sv \
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src/riscv-dbg/src/dm_pkg.sv \
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include/ariane_pkg.sv \
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include/std_cache_pkg.sv \
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include/wt_cache_pkg.sv \
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src/axi/src/axi_pkg.sv \
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src/register_interface/src/reg_intf.sv \
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src/register_interface/src/reg_intf_pkg.sv \
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include/axi_intf.sv \
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tb/ariane_soc_pkg.sv \
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include/ariane_axi_pkg.sv \
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src/fpu/src/fpnew_pkg.sv \
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src/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
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ariane_pkg := $(addprefix $(root-dir), $(ariane_pkg))
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# utility modules
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util := include/instr_tracer_pkg.sv \
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src/util/instr_tracer_if.sv \
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src/util/instr_tracer.sv \
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src/tech_cells_generic/src/cluster_clock_gating.sv \
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tb/common/mock_uart.sv \
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src/util/sram.sv
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ifdef spike-tandem
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util += tb/common/spike.sv
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endif
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util := $(addprefix $(root-dir), $(util))
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# Test packages
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test_pkg := $(wildcard tb/test/*/*sequence_pkg.sv*) \
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$(wildcard tb/test/*/*_pkg.sv*)
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# DPI
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dpi_list := $(patsubst tb/dpi/%.cc, ${dpi-library}/%.o, $(wildcard tb/dpi/*.cc))
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# filter spike stuff if tandem is not activated
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ifndef spike-tandem
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dpi = $(filter-out ${dpi-library}/spike.o ${dpi-library}/sim_spike.o, $(dpi_list))
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else
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dpi = $(dpi_list)
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endif
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dpi_hdr := $(wildcard tb/dpi/*.h)
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dpi_hdr := $(addprefix $(root-dir), $(dpi_hdr))
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CFLAGS := -I$(QUESTASIM_HOME)/include \
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-I$(RISCV)/include \
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-std=c++11 -I../tb/dpi
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ifdef spike-tandem
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CFLAGS += -Itb/riscv-isa-sim/install/include/spike
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endif
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# this list contains the standalone components
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src := $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv)) \
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$(filter-out src/fpu/src/fpnew_pkg.sv, $(wildcard src/fpu/src/*.sv)) \
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$(filter-out src/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv, \
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$(wildcard src/fpu/src/fpu_div_sqrt_mvp/hdl/*.sv)) \
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$(wildcard src/frontend/*.sv) \
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$(filter-out src/cache_subsystem/std_no_dcache.sv, \
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$(wildcard src/cache_subsystem/*.sv)) \
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$(wildcard bootrom/*.sv) \
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$(wildcard src/clint/*.sv) \
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$(wildcard fpga/src/axi2apb/src/*.sv) \
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$(wildcard fpga/src/axi_slice/src/*.sv) \
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$(wildcard src/axi_node/src/*.sv) \
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$(wildcard src/axi_riscv_atomics/src/*.sv) \
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$(wildcard src/axi_mem_if/src/*.sv) \
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src/rv_plic/rtl/rv_plic_target.sv \
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src/rv_plic/rtl/rv_plic_gateway.sv \
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src/rv_plic/rtl/plic_regmap.sv \
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src/rv_plic/rtl/plic_top.sv \
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src/riscv-dbg/src/dmi_cdc.sv \
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src/riscv-dbg/src/dmi_jtag.sv \
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src/riscv-dbg/src/dmi_jtag_tap.sv \
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src/riscv-dbg/src/dm_csrs.sv \
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src/riscv-dbg/src/dm_mem.sv \
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src/riscv-dbg/src/dm_sba.sv \
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src/riscv-dbg/src/dm_top.sv \
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src/riscv-dbg/debug_rom/debug_rom.sv \
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src/register_interface/src/apb_to_reg.sv \
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src/axi/src/axi_multicut.sv \
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src/common_cells/src/deprecated/generic_fifo.sv \
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src/common_cells/src/deprecated/pulp_sync.sv \
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src/common_cells/src/deprecated/find_first_one.sv \
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src/common_cells/src/rstgen_bypass.sv \
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src/common_cells/src/rstgen.sv \
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src/common_cells/src/stream_mux.sv \
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src/common_cells/src/stream_demux.sv \
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src/util/axi_master_connect.sv \
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src/util/axi_slave_connect.sv \
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src/util/axi_master_connect_rev.sv \
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src/util/axi_slave_connect_rev.sv \
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src/axi/src/axi_cut.sv \
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src/axi/src/axi_join.sv \
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src/axi/src/axi_delayer.sv \
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src/axi/src/axi_to_axi_lite.sv \
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src/fpga-support/rtl/SyncSpRamBeNx64.sv \
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src/common_cells/src/unread.sv \
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src/common_cells/src/sync.sv \
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src/common_cells/src/cdc_2phase.sv \
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src/common_cells/src/spill_register.sv \
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src/common_cells/src/sync_wedge.sv \
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src/common_cells/src/edge_detect.sv \
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src/common_cells/src/stream_arbiter.sv \
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src/common_cells/src/stream_arbiter_flushable.sv \
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src/common_cells/src/deprecated/fifo_v1.sv \
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src/common_cells/src/deprecated/fifo_v2.sv \
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src/common_cells/src/fifo_v3.sv \
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src/common_cells/src/lzc.sv \
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src/common_cells/src/popcount.sv \
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src/common_cells/src/rr_arb_tree.sv \
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src/common_cells/src/deprecated/rrarbiter.sv \
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src/common_cells/src/stream_delay.sv \
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src/common_cells/src/lfsr_8bit.sv \
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src/common_cells/src/lfsr_16bit.sv \
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src/common_cells/src/counter.sv \
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src/common_cells/src/shift_reg.sv \
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src/tech_cells_generic/src/pulp_clock_gating.sv \
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src/tech_cells_generic/src/cluster_clock_inverter.sv \
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src/tech_cells_generic/src/pulp_clock_mux2.sv \
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tb/ariane_testharness.sv \
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tb/ariane_peripherals.sv \
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tb/common/uart.sv \
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tb/common/SimDTM.sv \
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tb/common/SimJTAG.sv
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src := $(addprefix $(root-dir), $(src))
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uart_src := $(wildcard fpga/src/apb_uart/src/*.vhd)
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uart_src := $(addprefix $(root-dir), $(uart_src))
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fpga_src := $(wildcard fpga/src/*.sv) $(wildcard fpga/src/bootrom/*.sv) $(wildcard fpga/src/ariane-ethernet/*.sv)
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fpga_src := $(addprefix $(root-dir), $(fpga_src))
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# look for testbenches
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tbs := tb/ariane_tb.sv tb/ariane_testharness.sv
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# RISCV asm tests and benchmark setup (used for CI)
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# there is a definesd test-list with selected CI tests
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riscv-test-dir := tmp/riscv-tests/build/isa/
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riscv-benchmarks-dir := tmp/riscv-tests/build/benchmarks/
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riscv-asm-tests-list := ci/riscv-asm-tests.list
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riscv-amo-tests-list := ci/riscv-amo-tests.list
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riscv-mul-tests-list := ci/riscv-mul-tests.list
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riscv-fp-tests-list := ci/riscv-fp-tests.list
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riscv-benchmarks-list := ci/riscv-benchmarks.list
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riscv-asm-tests := $(shell xargs printf '\n%s' < $(riscv-asm-tests-list) | cut -b 1-)
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riscv-amo-tests := $(shell xargs printf '\n%s' < $(riscv-amo-tests-list) | cut -b 1-)
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riscv-mul-tests := $(shell xargs printf '\n%s' < $(riscv-mul-tests-list) | cut -b 1-)
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riscv-fp-tests := $(shell xargs printf '\n%s' < $(riscv-fp-tests-list) | cut -b 1-)
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riscv-benchmarks := $(shell xargs printf '\n%s' < $(riscv-benchmarks-list) | cut -b 1-)
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# Search here for include files (e.g.: non-standalone components)
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incdir := src/common_cells/include/
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# Compile and sim flags
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compile_flag += +cover=bcfst+/dut -incr -64 -nologo -quiet -suppress 13262 -permissive +define+$(defines)
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uvm-flags += +UVM_NO_RELNOTES +UVM_VERBOSITY=LOW
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questa-flags += -t 1ns -64 -coverage -classdebug $(gui-sim) $(QUESTASIM_FLAGS)
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compile_flag_vhd += -64 -nologo -quiet -2008
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# Iterate over all include directories and write them with +incdir+ prefixed
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# +incdir+ works for Verilator and QuestaSim
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list_incdir := $(foreach dir, ${incdir}, +incdir+$(dir))
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# RISCV torture setup
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riscv-torture-dir := tmp/riscv-torture
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# old java flags -Xmx1G -Xss8M -XX:MaxPermSize=128M
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# -XshowSettings -Xdiag
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riscv-torture-bin := java -jar sbt-launch.jar
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# if defined, calls the questa targets in batch mode
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ifdef batch-mode
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questa-flags += -c
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questa-cmd := -do "coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]"
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questa-cmd += -do " log -r /*; run -all;"
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else
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questa-cmd := -do " log -r /*; run -all;"
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endif
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# we want to preload the memories
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ifdef preload
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questa-cmd += +PRELOAD=$(preload)
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elf-bin = none
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endif
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ifdef spike-tandem
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questa-cmd += -gblso tb/riscv-isa-sim/install/lib/libriscv.so
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endif
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# remote bitbang is enabled
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ifdef rbb
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questa-cmd += +jtag_rbb_enable=1
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else
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questa-cmd += +jtag_rbb_enable=0
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endif
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# Build the TB and module using QuestaSim
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build: $(library) $(library)/.build-srcs $(library)/.build-tb $(dpi-library)/ariane_dpi.so
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# Optimize top level
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vopt$(questa_version) $(compile_flag) -work $(library) $(top_level) -o $(top_level)_optimized +acc -check_synthesis
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# src files
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$(library)/.build-srcs: $(util) $(library)
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vlog$(questa_version) $(compile_flag) -work $(library) $(filter %.sv,$(ariane_pkg)) $(list_incdir) -suppress 2583
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# vcom$(questa_version) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(ariane_pkg))
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vlog$(questa_version) $(compile_flag) -work $(library) $(filter %.sv,$(util)) $(list_incdir) -suppress 2583
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# Suppress message that always_latch may not be checked thoroughly by QuestaSim.
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vcom$(questa_version) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(uart_src))
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# vcom$(questa_version) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(src))
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vlog$(questa_version) $(compile_flag) -work $(library) -pedanticerrors $(filter %.sv,$(src)) $(list_incdir) -suppress 2583
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touch $(library)/.build-srcs
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# build TBs
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$(library)/.build-tb: $(dpi)
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# Compile top level
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vlog$(questa_version) $(compile_flag) -sv $(tbs) -work $(library)
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touch $(library)/.build-tb
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$(library):
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vlib${questa_version} $(library)
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# compile DPIs
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$(dpi-library)/%.o: tb/dpi/%.cc $(dpi_hdr)
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mkdir -p $(dpi-library)
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$(CXX) -shared -fPIC -std=c++0x -Bsymbolic $(CFLAGS) -c $< -o $@
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$(dpi-library)/ariane_dpi.so: $(dpi)
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mkdir -p $(dpi-library)
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# Compile C-code and generate .so file
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$(CXX) -shared -m64 -o $(dpi-library)/ariane_dpi.so $? -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -lfesvr
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# single test runs on Questa can be started by calling make <testname>, e.g. make towers.riscv
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# the test names are defined in ci/riscv-asm-tests.list, and in ci/riscv-benchmarks.list
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# if you want to run in batch mode, use make <testname> batch-mode=1
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# alternatively you can call make sim elf-bin=<path/to/elf-bin> in order to load an arbitrary binary
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sim: build
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vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +MAX_CYCLES=$(max_cycles) +UVM_TESTNAME=$(test_case) \
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+BASEDIR=$(riscv-test-dir) $(uvm-flags) $(QUESTASIM_FLAGS) -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
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${top_level}_optimized +permissive-off ++$(elf-bin) ++$(target-options) | tee sim.log
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$(riscv-asm-tests): build
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vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \
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+BASEDIR=$(riscv-test-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
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${top_level}_optimized $(QUESTASIM_FLAGS) +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-asm-tests-$@.log
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$(riscv-amo-tests): build
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vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \
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+BASEDIR=$(riscv-test-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
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${top_level}_optimized $(QUESTASIM_FLAGS) +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-amo-tests-$@.log
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$(riscv-mul-tests): build
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vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \
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+BASEDIR=$(riscv-test-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
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${top_level}_optimized $(QUESTASIM_FLAGS) +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-mul-tests-$@.log
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$(riscv-fp-tests): build
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vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \
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+BASEDIR=$(riscv-test-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
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${top_level}_optimized $(QUESTASIM_FLAGS) +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-fp-tests-$@.log
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$(riscv-benchmarks): build
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vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \
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+BASEDIR=$(riscv-benchmarks-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
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${top_level}_optimized $(QUESTASIM_FLAGS) +permissive-off ++$(riscv-benchmarks-dir)/$@ ++$(target-options) | tee tmp/riscv-benchmarks-$@.log
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# can use -jX to run ci tests in parallel using X processes
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run-asm-tests: $(riscv-asm-tests)
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$(MAKE) check-asm-tests
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run-amo-tests: $(riscv-amo-tests)
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$(MAKE) check-amo-tests
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run-mul-tests: $(riscv-mul-tests)
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$(MAKE) check-mul-tests
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run-fp-tests: $(riscv-fp-tests)
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$(MAKE) check-fp-tests
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check-asm-tests:
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ci/check-tests.sh tmp/riscv-asm-tests- $(shell wc -l $(riscv-asm-tests-list) | awk -F " " '{ print $1 }')
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check-amo-tests:
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ci/check-tests.sh tmp/riscv-amo-tests- $(shell wc -l $(riscv-amo-tests-list) | awk -F " " '{ print $1 }')
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check-mul-tests:
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ci/check-tests.sh tmp/riscv-mul-tests- $(shell wc -l $(riscv-mul-tests-list) | awk -F " " '{ print $1 }')
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check-fp-tests:
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ci/check-tests.sh tmp/riscv-fp-tests- $(shell wc -l $(riscv-fp-tests-list) | awk -F " " '{ print $1 }')
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# can use -jX to run ci tests in parallel using X processes
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run-benchmarks: $(riscv-benchmarks)
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$(MAKE) check-benchmarks
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check-benchmarks:
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ci/check-tests.sh tmp/riscv-benchmarks- $(shell wc -l $(riscv-benchmarks-list) | awk -F " " '{ print $1 }')
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# verilator-specific
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verilate_command := $(verilator) \
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$(filter-out %.vhd, $(ariane_pkg)) \
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$(filter-out src/fpu_wrap.sv, $(filter-out %.vhd, $(src))) \
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+define+$(defines) \
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src/util/sram.sv \
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+incdir+src/axi_node \
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$(if $(verilator_threads), --threads $(verilator_threads)) \
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--unroll-count 256 \
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-Werror-PINMISSING \
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-Werror-IMPLICIT \
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-Wno-fatal \
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-Wno-PINCONNECTEMPTY \
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-Wno-ASSIGNDLY \
|
|
-Wno-DECLFILENAME \
|
|
-Wno-UNUSED \
|
|
-Wno-UNOPTFLAT \
|
|
-Wno-style \
|
|
$(if $(PROFILE),--stats --stats-vars --profile-cfuncs,) \
|
|
$(if $(DEBUG),--trace --trace-structs,) \
|
|
-LDFLAGS "-L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -lfesvr$(if $(PROFILE), -g -pg,) -lpthread" \
|
|
-CFLAGS "$(CFLAGS)$(if $(PROFILE), -g -pg,)" -Wall --cc --vpi \
|
|
$(list_incdir) --top-module ariane_testharness \
|
|
--Mdir $(ver-library) -O3 \
|
|
--exe tb/ariane_tb.cpp tb/dpi/SimDTM.cc tb/dpi/SimJTAG.cc \
|
|
tb/dpi/remote_bitbang.cc tb/dpi/msim_helper.cc
|
|
|
|
# User Verilator, at some point in the future this will be auto-generated
|
|
verilate:
|
|
@echo "[Verilator] Building Model$(if $(PROFILE), for Profiling,)"
|
|
$(verilate_command)
|
|
cd $(ver-library) && $(MAKE) -j${NUM_JOBS} -f Variane_testharness.mk
|
|
|
|
sim-verilator: verilate
|
|
$(ver-library)/Variane_testharness $(elf-bin)
|
|
|
|
$(addsuffix -verilator,$(riscv-asm-tests)): verilate
|
|
$(ver-library)/Variane_testharness $(riscv-test-dir)/$(subst -verilator,,$@)
|
|
|
|
$(addsuffix -verilator,$(riscv-amo-tests)): verilate
|
|
$(ver-library)/Variane_testharness $(riscv-test-dir)/$(subst -verilator,,$@)
|
|
|
|
$(addsuffix -verilator,$(riscv-mul-tests)): verilate
|
|
$(ver-library)/Variane_testharness $(riscv-test-dir)/$(subst -verilator,,$@)
|
|
|
|
$(addsuffix -verilator,$(riscv-fp-tests)): verilate
|
|
$(ver-library)/Variane_testharness $(riscv-test-dir)/$(subst -verilator,,$@)
|
|
|
|
$(addsuffix -verilator,$(riscv-benchmarks)): verilate
|
|
$(ver-library)/Variane_testharness $(riscv-benchmarks-dir)/$(subst -verilator,,$@)
|
|
|
|
run-asm-tests-verilator: $(addsuffix -verilator, $(riscv-asm-tests)) $(addsuffix -verilator, $(riscv-amo-tests)) $(addsuffix -verilator, $(riscv-fp-tests)) $(addsuffix -verilator, $(riscv-fp-tests))
|
|
|
|
# split into smaller travis jobs (otherwise they will time out)
|
|
riscv-asm-rv64ui-v := $(filter rv64ui-v-%, $(riscv-asm-tests))
|
|
|
|
riscv-asm-rv64ui-p := $(filter rv64ui-p-%, $(riscv-asm-tests))
|
|
|
|
riscv-asm-rv64mi-p := $(filter rv64mi-p-%, $(riscv-asm-tests))
|
|
|
|
riscv-asm-rest := $(filter-out $(riscv-asm-rv64ui-v) $(riscv-asm-rv64ui-p) $(riscv-asm-rv64mi-p), $(riscv-asm-tests))
|
|
|
|
run-asm-tests1-verilator: $(addsuffix -verilator, $(filter rv64ui-v-a% rv64ui-v-b%, $(riscv-asm-rv64ui-v)))
|
|
|
|
run-asm-tests2-verilator: $(addsuffix -verilator, $(filter-out rv64ui-v-a% rv64ui-v-b%, $(riscv-asm-rv64ui-v)))
|
|
|
|
run-asm-tests3-verilator: $(addsuffix -verilator, $(filter rv64ui-p-a% rv64ui-p-b%, $(riscv-asm-rv64ui-p)))
|
|
|
|
run-asm-tests4-verilator: $(addsuffix -verilator, $(filter-out rv64ui-p-a% rv64ui-p-b%, $(riscv-asm-rv64ui-p)))
|
|
|
|
run-asm-tests5-verilator: $(addsuffix -verilator, $(riscv-asm-rv64mi-p))
|
|
|
|
run-asm-tests6-verilator: $(addsuffix -verilator, $(riscv-asm-rest))
|
|
|
|
run-amo-verilator: $(addsuffix -verilator, $(riscv-amo-tests))
|
|
|
|
riscv-amo-rv64ua-v := $(filter rv64ua-v-%, $(riscv-amo-tests))
|
|
|
|
riscv-amo-rv64ua-p := $(filter rv64ua-p-%, $(riscv-amo-tests))
|
|
|
|
run-amo-tests1-verilator: $(addsuffix -verilator, $(filter rv64ua-v-amom%, $(riscv-amo-rv64ua-v)))
|
|
|
|
run-amo-tests2-verilator: $(addsuffix -verilator, $(filter-out rv64ua-v-amom%, $(riscv-amo-rv64ua-v)))
|
|
|
|
run-amo-tests3-verilator: $(addsuffix -verilator, $(riscv-amo-rv64ua-p))
|
|
|
|
run-mul-verilator: $(addsuffix -verilator, $(riscv-mul-tests))
|
|
|
|
run-fp-verilator: $(addsuffix -verilator, $(riscv-fp-tests))
|
|
|
|
run-benchmarks-verilator: $(addsuffix -verilator,$(riscv-benchmarks))
|
|
|
|
# torture-specific
|
|
torture-gen:
|
|
cd $(riscv-torture-dir) && $(riscv-torture-bin) 'generator/run'
|
|
|
|
torture-itest:
|
|
cd $(riscv-torture-dir) && $(riscv-torture-bin) 'testrun/run -a output/test.S'
|
|
|
|
torture-rtest: build
|
|
cd $(riscv-torture-dir) && printf "#!/bin/sh\ncd $(root-dir) && $(MAKE) run-torture$(torture-logs) batch-mode=1 defines=$(defines) test-location=$(test-location)" > call.sh && chmod +x call.sh
|
|
cd $(riscv-torture-dir) && $(riscv-torture-bin) 'testrun/run -r ./call.sh -a $(test-location).S' | tee $(test-location).log
|
|
make check-torture test-location=$(test-location)
|
|
|
|
torture-dummy: build
|
|
cd $(riscv-torture-dir) && printf "#!/bin/sh\ncd $(root-dir) && $(MAKE) run-torture batch-mode=1 defines=$(defines) test-location=\$${@: -1}" > call.sh
|
|
|
|
torture-rnight: build
|
|
cd $(riscv-torture-dir) && printf "#!/bin/sh\ncd $(root-dir) && $(MAKE) run-torture$(torture-logs) batch-mode=1 defines=$(defines) test-location=\$${@: -1}" > call.sh && chmod +x call.sh
|
|
cd $(riscv-torture-dir) && $(riscv-torture-bin) 'overnight/run -r ./call.sh -g none' | tee output/overnight.log
|
|
$(MAKE) check-torture
|
|
|
|
torture-rtest-verilator: verilate
|
|
cd $(riscv-torture-dir) && printf "#!/bin/sh\ncd $(root-dir) && $(MAKE) run-torture-verilator batch-mode=1 defines=$(defines)" > call.sh && chmod +x call.sh
|
|
cd $(riscv-torture-dir) && $(riscv-torture-bin) 'testrun/run -r ./call.sh -a output/test.S' | tee output/test.log
|
|
$(MAKE) check-torture
|
|
|
|
run-torture: build
|
|
vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles)+UVM_TESTNAME=$(test_case) \
|
|
+BASEDIR=$(riscv-torture-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
|
|
${top_level}_optimized +permissive-off +signature=$(riscv-torture-dir)/$(test-location).rtlsim.sig ++$(riscv-torture-dir)/$(test-location) ++$(target-options)
|
|
|
|
run-torture-log: build
|
|
vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles)+UVM_TESTNAME=$(test_case) \
|
|
+BASEDIR=$(riscv-torture-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
|
|
${top_level}_optimized +permissive-off +signature=$(riscv-torture-dir)/$(test-location).rtlsim.sig ++$(riscv-torture-dir)/$(test-location) ++$(target-options)
|
|
cp vsim.wlf $(riscv-torture-dir)/$(test-location).wlf
|
|
cp trace_hart_0000.log $(riscv-torture-dir)/$(test-location).trace
|
|
cp trace_hart_0000_commit.log $(riscv-torture-dir)/$(test-location).commit
|
|
cp transcript $(riscv-torture-dir)/$(test-location).transcript
|
|
|
|
run-torture-verilator: verilate
|
|
$(ver-library)/Variane_testharness +max-cycles=$(max_cycles) +signature=$(riscv-torture-dir)/output/test.rtlsim.sig $(riscv-torture-dir)/output/test
|
|
|
|
check-torture:
|
|
grep 'All signatures match for $(test-location)' $(riscv-torture-dir)/$(test-location).log
|
|
diff -s $(riscv-torture-dir)/$(test-location).spike.sig $(riscv-torture-dir)/$(test-location).rtlsim.sig
|
|
|
|
fpga_filter := $(addprefix $(root-dir), bootrom/bootrom.sv)
|
|
fpga_filter += $(addprefix $(root-dir), include/instr_tracer_pkg.sv)
|
|
fpga_filter += $(addprefix $(root-dir), src/util/ex_trace_item.sv)
|
|
fpga_filter += $(addprefix $(root-dir), src/util/instr_trace_item.sv)
|
|
fpga_filter += $(addprefix $(root-dir), src/util/instr_tracer_if.sv)
|
|
fpga_filter += $(addprefix $(root-dir), src/util/instr_tracer.sv)
|
|
|
|
fpga: $(ariane_pkg) $(util) $(src) $(fpga_src) $(uart_src)
|
|
@echo "[FPGA] Generate sources"
|
|
@echo read_vhdl {$(uart_src)} > fpga/scripts/add_sources.tcl
|
|
@echo read_verilog -sv {$(ariane_pkg)} >> fpga/scripts/add_sources.tcl
|
|
@echo read_verilog -sv {$(filter-out $(fpga_filter), $(util))} >> fpga/scripts/add_sources.tcl
|
|
@echo read_verilog -sv {$(filter-out $(fpga_filter), $(src))} >> fpga/scripts/add_sources.tcl
|
|
@echo read_verilog -sv {$(fpga_src)} >> fpga/scripts/add_sources.tcl
|
|
@echo "[FPGA] Generate Bitstream"
|
|
cd fpga && make BOARD="genesys2" XILINX_PART="xc7k325tffg900-2" XILINX_BOARD="digilentinc.com:genesys2:part0:1.1" CLK_PERIOD_NS="20"
|
|
|
|
.PHONY: fpga
|
|
|
|
build-spike:
|
|
cd tb/riscv-isa-sim && mkdir -p build && cd build && ../configure --prefix=`pwd`/../install --with-fesvr=$(RISCV) --enable-commitlog && make -j8 install
|
|
|
|
clean:
|
|
rm -rf $(riscv-torture-dir)/output/test*
|
|
rm -rf $(library)/ $(dpi-library)/ $(ver-library)/
|
|
rm -f tmp/*.ucdb tmp/*.log *.wlf *vstf wlft* *.ucdb
|
|
|
|
.PHONY:
|
|
build sim sim-verilate clean \
|
|
$(riscv-asm-tests) $(addsuffix _verilator,$(riscv-asm-tests)) \
|
|
$(riscv-benchmarks) $(addsuffix _verilator,$(riscv-benchmarks)) \
|
|
check-benchmarks check-asm-tests \
|
|
torture-gen torture-itest torture-rtest \
|
|
run-torture run-torture-verilator check-torture check-torture-verilator
|
|
|